The dynamic power shrinks as process technology scale down

[Josephchiang]

Hello all,

I know that the topic seem not suitable for this board due to it is more related to digital circuit.

But I think this topic could be simply as "How does the parasitic capacitance shrinks as process scale down? "

So, Those who good at design Analog circuit design must know(or care) device parasitic capacitance very well.



The dynamic power consumption of digital circuit could be expressed as following equation

P=0.5*f*C*V^2, where f is operation frequency , C is parasitic capacitance of gate device , V is voltage.

If the process scale down from 90 nm to 65 nm , assume operation frequency and voltage same as older process and how much power I could saving in digital circuit.

If I only take care dynamic power and ignore the static power (leakage)

Base on the above equation. It looks like the power consumption is only related to the parasitic capacitance .

If I could well know the parasitic capacitance shrink ration then I could get the dynamic power consumption precisely.

But how could I get this information? Could I roughly estimate the shrink ration is 65 nm/90nm or have any rule of thumb principle.

Thank you for your help.

 

[dick_freebird]

Not all things shrink the same or at the same pace. The
explicit channel (thin ox under poly) shrinks fastest. The
overlap capacitances, less so and varying by the flow a
lot (engineered source & drain features like spacer and
LDD/halo combo). Then you have the interconnect stack
which doesn't scale as fast as the channel, held back by
via lithography and linewidth control across much larger
extents and more variable topography than the FEOL
gate process.

If you look at output load in a real chip it's not often
dominated by Tox capacitance anymore.

 

[c_mitra]

P=0.5*f*C*V^2, where f is operation frequency , C is parasitic capacitance of gate device , V is voltage.

.

You are in the right direction. But the scaling in not linear in all the cases. C depends on the area and the thickness of the dielectric. The thickness is not changed much but the area decreases as a square of the linear scaling parameter.

Just a rough example: consider the linear scaling is by a factor of 2.

C will decrease by a factor of 4. For the same power, you can increase f by a factor of 4.

However, with linear scaling by a factor of 2, the power cannot be kept constant. But smaller size has better power dissipation (greater surface to volume)- the actual dependence is rather complex.

Actually power consumption will decrease by a factor of 2. Then the frequency will actually increase by a factor 2 (not for) but the details are approximate.

Power consumption will depend also on frequency, voltage and capacitance. It is better to reduce the voltage because that is quadratic term,

 

[Josephchiang]

You are in the right direction. But the scaling in not linear in all the cases. C depends on the area and the thickness of the dielectric. The thickness is not changed much but the area decreases as a square of the linear scaling parameter.

Just a rough example: consider the linear scaling is by a factor of 2.

C will decrease by a factor of 4. For the same power, you can increase f by a factor of 4.

However, with linear scaling by a factor of 2, the power cannot be kept constant. But smaller size has better power dissipation (greater surface to volume)- the actual dependence is rather complex.

Actually power consumption will decrease by a factor of 2. Then the frequency will actually increase by a factor 2 (not for) but the details are approximate.

Power consumption will depend also on frequency, voltage and capacitance. It is better to reduce the voltage because that is quadratic term,

Hi C_mitra,

Thank you for your reply. You explain it very well but I still have some question about your reply

In your example, the linear scaling by a factor of 2 and the corresponding parasitic capacitance shrink by a ratio of 4.

But why does the power consumption decrease by a factor of 2 only rather than 4?

Does it exist other terms that will affect the result?

Would you please explain more detail about it. Thanks a million.

 

[c_mitra]

My explanation is rather crude and qualitative.

Scaling linearly by a factor of 2 decreases the capacitor surface area by 4; I assume that the dielectric layer thickness is not changed.

For the same power, the frequency can be increased by a factor of 4.

By the way, if the same power is applied into a smaller region, the temp rise will be unacceptable. Hence we have to reduce the power. But how much?

A small region cools faster, because it has a greater surface to volume proportion. (a spoon of hot water cools faster than a bucket of water). To keep the same core temp, we can now have greater power applied to the same region.

We cannot apply the same power to the smaller area or volume; we need to scale down. The actual formula depends on shape and other factors. I used a factor of 2 as an example.

I hope I am clearer now.

 

[Josephchiang]

Thanks a million again for such a clear explanation.