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Hi, I try to check the sram from tsmc's memory compiler mc2, by .gds and .spi, but the LVS reports give a mismatch error.
The SRAM is tsdn28hpcpa256x32m4mwa, and I disable some options when generting it, like BIST function..., the LVS report is :
Some warnings presented when running LVS:
I...
Hi, I am trying to simulate a SRAM's function, which comes from MC2 software.
My original aim is to wrapper the SRAM to what I want, a sram with 1rw1r and related parameters are 32_256_8.
I mean, I want a commercial SRAM from MC2 to replace the open_sram(Open_SRAM_sky130).
So, I generate a dual...
Many thanks for your response!
But I am confused what the relationship is between the techfile and lef, or the relationship between lef generator and DRC rules.
The point I dont understand is what does the lef generator utility do to match the stacks, just changing the DRC rules for different...
Hi,
I am using TSMC 28hpc digital PDK to design some circuits.
When I running the DRC, I found some DRC errors because the spacing, and finally, I found the techfiles that innovus used is different from the DRC rule.
In DRC rules, the Vertical Route Pitch is 0.14, but in the techfiles, TSMC...
Hi, I am trying to generate a ram from tsmc's memory compiler, but it looks the license cannot load correctly.
I typed ./lmgrd -c XXXXX/license.dat
and verify the status by the code ./lmutil lmpath -status
and get the result as the figure, it seems the license loaded but the lmutil cannot...
Hi, I am tring to simulate a design, but i found some different result. I dotn know why?
Here is a simple.
Verilog code:
module top(input wire clk, input wire [27:0] io_in, output wire [27:0] io_out, io_oeb);
wire rst = io_in[0];
reg [15:0] ctr;
always @(posedge clk)
if...
Thanks for your reply, the clock is indeed wrong. I found the solution when put the
initila begin
$fsdbDumpfile("adder_tb.fsdb");
$fsdbDumpvars(0,adder_tb);
$fsdbDumpSVA();
$fsdbDumpMDA();
$vcdpluson;
$vcdplusmemon;
end
behind the first "initial" block...
Hi, I'm tring to simulate a simple design adder, but when simulation, the CLK signal stay 0 so that no wave for me debug. Can you help me?
My codes and script are shown as below,
Adder module:
module top(input wire clk, input wire [27:0] io_in, output wire [27:0] io_out, io_oeb);
wire rst =...
hi, i am synthesis a dsp module from eFPGA. And as a simliar architecture compared with FPGA, there some combinational loops in this module, so i want to break them.
I found some detailed description in a paper: https://dl.acm.org/doi/10.1145/3024063 . And it described at page 10 as:
That must...
Hi, i am synthzing some modules, but it report some timing arc, so i want to try 'set_disable_timing', and to see whether these loop add the delay. I am not repair the RTL codes firstly because the codes has been synthesys correctly with a good timing but i am not now.
However, i kown...
Thanks. I type check_timing after compile, but it still exists loop, is there some way to fix it(when RTL codes dont have combinational loop but compileOutcome have)?
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