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Recent content by john.zhang

  1. J

    Large Signal Stability Analysis

    Hi all, I am designing a doubler with an input buffer. the Doubler itself is running with a bias near cut-off and using a push-push structure, while the input buffer is a simple CS structure. When I check stability, I often use the S probe in cadence environment, and the SP probe in ADS...
  2. J

    Cadence Sprobe stabindex

    do you have any tips for stability checks for multi stage amplifiers?
  3. J

    Cadence Sprobe stabindex

    Hi all, I am designing a two stage LNA, and so I am using the Sprobe to check for the stability. there is a "stab index" function in the sprobe for the sp analysis, however I am unsure how to use it. For stability FACTOR, I know it has to be greater than 1, and my circuit indeed does have...
  4. J

    LNA Stability

    I am designing an LNA for 30 to 45 GHz using SOI CMOS. I am using cadence virtuoso to simulate it, while my passive devices are EM simulated on ADS. All the guides I see online, usually start their SP analysis at 1 GHz, and so I also do that, and everything is fine. However, I recently tried to...
  5. J

    Cadence "swap sweep var" for all values of X

    Hi, I am on cadence virtuoso. I have a plot of S parameters, basically I swept 12 bits, so 4096 control states in the sp analysis, and I did a parametric on the frequency as this is faster than sweeping the frequency in sp analysis and then doing 4096 parametric simulations. But now, I have...
  6. J

    Zsopt invarianve with source degeneration

    Hi all, I am currently designing a simple LNA, and I have come across the statement that Zsopt does not change with the addition of a source degeneration Inductor. I heard the explanation that this is because Zsopt is invariant to lossless impedance transformations. However, when I try to...
  7. J

    How to plot NF vs RF Frequency in cadence

    Hi, I am designing a down conversion mixer which takes in an input RF freq of 70 to 80Ghz, however when I try to plot the NF, it's only possible to get NF vs output frequency plot, will it be possible to get the NF vs RF Freq plot? thanks
  8. J

    Inverters as Level Shifter with HVT and LVT transistors

    isnt that the same with the normal operation of the inverter? How does this compare with a latched level shifter?
  9. J

    Inverters as Level Shifter with HVT and LVT transistors

    Hi All, In my design I need to shift a 0.4V signal clock to a 1.2V signal clock, the clock is a ring osc with a 0v4 supply. I implemented two inverters in cascade as level shifters, with the first stage inverter having an HVT pmos and an LVT nmos, while the second stage are just normal pmos...
  10. J

    Probing with oscilloscope causes current drop

    We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto one of the pin outs of the chip (i.e. the ring oscillator and the clock), we detect a...

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