Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
I am designing a doubler with an input buffer. the Doubler itself is running with a bias near cut-off and using a push-push structure, while the input buffer is a simple CS structure. When I check stability, I often use the S probe in cadence environment, and the SP probe in ADS...
Hi all,
I am designing a two stage LNA, and so I am using the Sprobe to check for the stability.
there is a "stab index" function in the sprobe for the sp analysis, however I am unsure how to use it. For stability FACTOR, I know it has to be greater than 1, and my circuit indeed does have...
I am designing an LNA for 30 to 45 GHz using SOI CMOS. I am using cadence virtuoso to simulate it, while my passive devices are EM simulated on ADS. All the guides I see online, usually start their SP analysis at 1 GHz, and so I also do that, and everything is fine.
However, I recently tried to...
Hi,
I am on cadence virtuoso.
I have a plot of S parameters, basically I swept 12 bits, so 4096 control states in the sp analysis, and I did a parametric on the frequency as this is faster than sweeping the frequency in sp analysis and then doing 4096 parametric simulations.
But now, I have...
Hi all,
I am currently designing a simple LNA, and I have come across the statement that Zsopt does not change with the addition of a source degeneration Inductor.
I heard the explanation that this is because Zsopt is invariant to lossless impedance transformations. However, when I try to...
Hi,
I am designing a down conversion mixer which takes in an input RF freq of 70 to 80Ghz, however when I try to plot the NF, it's only possible to get NF vs output frequency plot, will it be possible to get the NF vs RF Freq plot?
thanks
Hi All,
In my design I need to shift a 0.4V signal clock to a 1.2V signal clock, the clock is a ring osc with a 0v4 supply.
I implemented two inverters in cascade as level shifters, with the first stage inverter having an HVT pmos and an LVT nmos, while the second stage are just normal pmos...
We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto one of the pin outs of the chip (i.e. the ring oscillator and the clock), we detect a...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.