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Hi All,
I have a questioned,
1. Where can we get layout databases (GDSII stream) which are free IP , that can uses for research, study and evaluation? Does any foundry, EDA firms or ARM provide such IP? Anywhere from 90nm --> 45nm.
2. Where can I download or get process development kit which is...
DFM issue ?
What is the process you working at?
From 130nm and below to nano world, DFM is getting increasinly more.
Its not really a design rules but more as a guidelines which we could fix it oppurtunistically to help improved the circuitry performances, yield, reliability, variation , and...
gds
Abbreviation is mentioned by ramz,
It is industrial format standard for layout design database.
For more info:
https://en.wikipedia.org/wiki/GDSII
There are many documentations about it, comparisons with OASIS and even Perl modules which useful. Search around the web.
You can use the SKILL to call the scripts that you want to point and execution them background. ( guess you TCL/TK scripts will source something that you need).
mentor graphics svrf file
Most of the sample syntaxs on basics DRC and LVS is available from the manual/user-guides.
This is depends which verification sign-off tool you are using.
Most of the time this is provided by your Foundry as part of the PDK suites.
OR provided by your company...
DRC
Design Rules Specs ( I believe you are refering layout sign-off) are usually defined by Foundries/Fabs and based on the process complexity ( which sub-micron category).
technology libraries is more on tech files which important for layer mappings, conversions, layers assigns for de factor...
rule deck format
Cadence format ( from the past till now ) might exist Diva, Assura and Dracula I believe,
There are tools to convert in between Hercules runset formats to some of them above,
Try contact your EDA vendor AE. This is written in some manual and even some older manual of Hercules too.
dracula verification tool
All this are physical verification tools from different vendors ( Assura/Dracula -> Cadence ), Calibre from Mentor and Hercules from Synopsys.
Each of them have their own pros/cons, syntaxs, capabilities, functionalities and supported formats ( own formats).
This...
Are you using Calibre LVS device-Extraction (output should be AGF) or you are using Hercules LVS for the device-extraction. ( output XTR View MW).
What I mean "extraction" here is device extraction to create annotated databases ( including LVS ). Not the parasitic extraction.
what is dummy?
Dummy in sense of bonus cells.... that are layers that doped into the layout with NO layout functionality to the layout. Its used to improve the yield during fabrication , improves reliability of the chip.
Hi all,
I see many cases written for example like
The DRC is "Clean by Construction".
And sometimes is "Clean by Design"...
There are still something called "Clean by ....." pls do post it here. I would like to know....
Ok, the questions is.. what to this terms really mean???
Thanks
gdsii dump
GDSII is the worldwide recognize format to store layout design data. Its in binary form.
if you using unix,
od -h file.gds can view it hexa form.
anyway there is alot of free scripts to let you dump the GDS into ASCII/Text enable to let you see all the coordinates and datatype of...
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