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In fifo by using gray code pointers we can cross easily in between two clock domains. Because there will be a single bit transition only. But my questions is...
If write is faster clock & read is slower clock. There may be a chance that write pointer increments more than once in between read...
write clk is 100mhz and is writing into a fifo with the rate 60/100 ; read clk is 60Mhz and is reading from the fifo with the rate 60/80 , Then what is the fifo depth...?
Please anybody help me.... :(
If you use "single process/always which is synchronous" to develop your FSM, mealy is preferrable to reduce number of states and latency.
for example: (VHDL)
MOORE:
--------
process(clk)begin
if(clk'event and clk = '1')then
case my_state is
when "00" => if( a = '0')then...
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