which is preferable b/w moore & mealy

[jny]

If you use "single process/always which is synchronous" to develop your FSM, mealy is preferrable to reduce number of states and latency.

for example: (VHDL)
MOORE:
--------

---

Code VHDL - [expand]
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process(clk)begin
if(clk'event and clk = '1')then
   case my_state is
   when "00" => if( a = '0')then
                         my_state <= "01";
                      end if;
                      y <= "000";
   when "01" => if(a = '1')then
                         my_state <= "10";
                      end if;
                      y <= "001";
   when "10" => if(a = '0')then
                         my_state <= "11";
                      end if;
                      y <= "010";
   when "11" => if(a = '1')then
                          my_state <= "00";
                      end if;
                      y <= "100";
   end case;
end if;
end process;

---

MEALY:
-------

---

Code VHDL - [expand]
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process(clk)begin
if(clk'event and clk = '1')then
   case my_state is
   when "00" => if( a = '0')then
                         my_state <= "01";
                         y <= "001";
                      end if;
   when "01" => if(a = '1')then
                         my_state <= "10";
                         y <= "010";
                      end if;
                      
   when "10" => if(a = '0')then
                         my_state <= "11";
                         y <= "100";
                      end if;
                      
   when "11" => if(a = '1')then
                         my_state <= "00";
                         y <= "000";
                      end if;                  
   end case;
end if;
end process;

---

If you write like this both moore & mealy are synchronous.
I prefer mealy.

correct me if i'm wrong...

 

[std_match]

I wish that people could stop talking about Moore and Mealy state-machines, because neither of them describe what we normally do today. Both of them have combinatorial logic after the registers, and that is not wanted with today's FPGA/ASIC architectures. They both have "input logic", registers and "output logic". The difference is that the Moore machine uses only the registers as input to the output logic, while the Mealy machine also routes the input signals to the output logic.

Since we normally don't have "output logic" today (as in your examples), we can not say that it is a Moore or Mealy machine. What you call "MEALY" above is the logical thing to do with modern FPGA/ASIC architectures, and what you call "MOORE" has a meaningless one clock cycle delay for the output signals.

What we do today could maybe be described as "Mealy plus output registers" or "Moore without output logic". IMHO, strict Mealy or Moore machines are only useful if you want to minimize the number of registers. Registers are cheap now.

 

[yadavvlsi]

Please check below link:
https://www.evlsi.com/viewtopic.php?f=12&t=53