If write pointer increments more than once in b/w read clock edges

[jny]

In fifo by using gray code pointers we can cross easily in between two clock domains. Because there will be a single bit transition only. But my questions is...
If write is faster clock & read is slower clock. There may be a chance that write pointer increments more than once in between read clock edges. So, gray code will have multi bit transition. With this multi bit transition don't we get data incoherency problem..?

 

[ud23]

https://www.iosrjournals.org/iosr-jvlsi/papers/vol1-issue3/E0133237.pdf