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My synthesis was successful initially(on both 32-bit and 64-bit machine) when I used standard-cell to implement my small register file. Because I have 128 instances of that, I ran into power issue and convert them to compiled memory module, only then I ran into problem. I agreed , perhaps the...
I have a >5M gate design, and I ran into memory problem while synthesizing on amd64, Linux 64-bit machine with 4GB RAM. It had exhausted all the available memory and also run into swap, and had ttaken very long time to synthesize. I had a feeling it was due to the Linux OS, anyone encounter the...
Some memory compilers cannot generate memories of very small configurations, eg. 8X32 or 16X16. I was thinking of whether Module Compiler can be configured to use specialized cells(Register File cells) available in the standard-cell library and generate them that are area and timing efficient...
synopsys covermeter + how to invoke it
Modelsim also provide code coverage covering statements, branch, expression and toggle coverage. I find it quite user friendly, just need to compile with the coverage options that you want and then simulate by turning on coverage, interactively or script...
Anyone experience in using module compiler to create a custom register file from some specialized regfile cells in the standard-cell library (eg. UMC lib)?
Thanks.
If you are a registered user of Synopsys Design-Compiler, just visit the Solvenet site and explore what you want to know, things that you won't be able to find an answer in books.
If you've done a good job in handling the exchanges of data between different clock domain, perhaps using an asynchronous fifo for that. Then you can safely set false paths between the asynchronous clocks.
In DC, the memory instantiated in the VHDL file will be treated as black box, do not read the behavorial model of the memory in DC, as they will not be recognized and synthesized. The timing arcs and area are defined in the .lib/.db, you will be able to performed pre-layout timing verification...
I run vmware(linux) on win2000, it working really fine, provided you have enough memory on your machine. But, running complex applications/tools like design compiler synthesizing a relatively large design can cause your virtual machine to run into swap, and will take ages to complete the synthesis.
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