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You can't check DDR SDRAM interface timing using
STAMP models, or any other Primetime models for
that matter. In order to get good results the IO timing needs to be simulated using a good model
of the bonding wire, package trace and board trace
behaviour, using spice in order to determine if the
IO timing is met. Primetime is meant to be used for
on chip timing mainly, certainly not fast interfaces
like DDR SDRAM.