Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

STAMP model for DDR SDRAM?

Status
Not open for further replies.

jkfoo

Member level 1
Joined
May 17, 2001
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
261
.lib stamp

Has anyone familiar with or ever come across a STAMP model for DDR SDRAM?
 

eternal_nan

Full Member level 3
Joined
Mar 10, 2003
Messages
156
Helped
26
Reputation
52
Reaction score
10
Trophy points
1,298
Location
eternity
Activity points
1,412
You can't check DDR SDRAM interface timing using
STAMP models, or any other Primetime models for
that matter. In order to get good results the IO timing needs to be simulated using a good model
of the bonding wire, package trace and board trace
behaviour, using spice in order to determine if the
IO timing is met. Primetime is meant to be used for
on chip timing mainly, certainly not fast interfaces
like DDR SDRAM.
 

sri1502

Newbie level 3
Joined
Jan 5, 2005
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
72
Hi
I also heard few people talking about stamp model or .lib model to check DDR timing. I haven't come across anyone who actually did it successfully.

I also attempted to create a stamp model or some kind of model to check DDR io timings, I was not successful too, so I ended up checking in a traditional way

Let me know if you are interested to know the problems I faced?
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top