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the 4kT/Cs is the thermal noise of switch on-resistance only. one kT/Cs comes from the sample phase, and another kT/Cs from amplification phase, so 2kT/Cs. then it is twice due to fully-differential structure. for accuracy calculation during the amplification phase the noise is also the function...
for a conservative designer the thermal noise due to switch is 4kT/Cs for sample and amplification phase and fully-differential structure.
the on-resistance of switch slows the speed of amplifier, BWeff=BWorig/(1+gm*Ron).
Re: A Question About Calculating FFT in Delta Sigma Modulato
that is spectral leakage from the signal.
the point number that is added up to get the signal power depend on the used window. three points for hanning window.
hi aaronwlee,
a method is to measure the ratio of PTAT voltage to bandgap reference voltage using an adc.
see this paper:
A CMOS Smart Temperature Sensor With a 3σ Inaccuracy of +/-0.1°C From -55°C to 125°C - Michiel A. P. Pertijs
two stage two separate cmfb
hi sj_helen,
in a two-stage amplifier, one method is to use two cmfb, and the other method is to use one cmfb with an inversion stage.
Re: How can I deal with 3rd HD in a 2nd SigmaDelta Modulator
hi DZC,
firstly, maybe the slew rate is too small, so increase it and try again.
do you use multibit quantizer?
from your psd the resolution of 16 bits is difficult to achieve.
hi naalald,
maybe the time points is problematical, try the time period 2m+1/63131 ~ 1.002, or 2m-0.1/63131 ~ 1.002-0.1/63131. if bad yet, export the data and run fft in matlab. luck.
cmos comparator circuit design
hi sandhaajith,
the offset and hysteresis requirements of the comparator in sigma-delta modulator is relaxed and the high-speed is required, so it can be designed with a preamplifier followed by a latch with reset.
see this paper:
“A High-Speed CMOS Comparator...
Re: high resolution (15 bit) delta sigma ADC simulation prob
it is continuous-time sigma-delta modulator you have modelled? what about psd you have got? what difference compared to that from cadence? try errpreset=convative as well.
well, i think the maximum SNDR is more important. but in your case, you can select a input amplitude close to the input amplitude with which the maximum SNDR is obtained to reduce the testing time.
hi taik,
the first plot is right.
you should ensure that CLK1 and CLK2 are the non-overlapped clocks firstly.
just simulate it using transient analysis and check the operating point of opamp and the output.
hi, tony_taoyh
it is difficult to set the gain of vcvs. my suggestion is to use the ct-cmfb replacing the sc-cmfb, and set the resistors enough large. retain the hold capacitors between output and bias_cm.
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