CMOS comparator for sigma delta ADC

[sandhaajith]

cmos comparator

Can anyone suggest how to design a comparator for sigma delta ADC

 

[jiangxb]

cmos comparator circuit design

hi sandhaajith,

the offset and hysteresis requirements of the comparator in sigma-delta modulator is relaxed and the high-speed is required, so it can be designed with a preamplifier followed by a latch with reset.

see this paper:
“A High-Speed CMOS Comparator with 8-b Resolution,” IEEE J. of Sold-State Circuits Feb.1992, pp.208-211.

 

[iexplorer]

comparator sigma delta

really?
I think comparator nonlinearity is a key issue in sigma delta design, because it can not be attenuated
by loop, is itn't

 

[jcpu]

cmos sigma-delta modulator of adc

What does it mean by "comparator nonlinearity"?
Please explain more...
Thanks

 

[sandhaajith]

design cmos comparator

i understand that comparator non linearities are
offset
metastability
memory effect
kickback noise
overdrive recovery
to name a few

Added after 1 minutes:

can u tell me how to select ucox for a mosfet?

 

[ytliang]

cmos comparator resolution

What does it mean by "comparator nonlinearity"?
Please explain more...
Thanks

Linear circuits are circuits whose input signals are linearly related to the circuit's output. e.g.
X -> Y
aX -> aY

I dont think comparators are linear in the first place. For example,
X -> Y
aX -> Y