MASH (2-1 cascade) Design Question

[skythunder]

Hi. guys,

I want to design a third-order delta-sigma adc and I want to try MASH(multi-stage noise shaping) structure with 2-1 cascade. The behavioral model is shown below.

I have question about the noise cancellation logic. How do I realize the gain block
"1/c1" and "b1-1" . I think the two quantizer outputs y1 and y2 are signle-bit data,
what it will be like when they pass the "1/c1" and "b1-1" ?

The D block is simply realized by a D-Flipflop ("1/z"), while XOR gate can be used to realize ("1-1/z").

 

[jiangxb]

hi skythunder,

noise cancellation logic should be implemented by digital logic circuit. gain is performed by simple shiftting bit.