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Hi Puppet1,
I visualize the given opamp configuration as "Two stage Opamp design with Miller Cap compensation".
I have attached the reference image.
Since the added Cc introduces a "Right hand side zero" the phase margin can be less than required.
So, it has a higher possibility to...
Hi,
Finally I am able to model it using LAPLACE equation.
Glaplace p n LAPLACE {V(p,n)} {s*C} ==> This implements a voltage controlled current source with a transfer function of I(s) = V(s) * s * C.
I find this implementation is useful,
1.When anybody wants to convert a Hspice capacitance...
Hi,
The question is related to Pspice modeling.
I want to model a capacitor using the equation Q = C*V.
The reason behind this implementation is,
1. I can access the voltage across this charge source.
2. I can model a capacitance which has the dependency on the voltage across it.
In...
Hi,
I just wanted to simulate and see the advantage of "Bottom Plate Sampling".
So, I have put the circuit as shown in attachment and simulated. The waveform is shown adjacent to the circuit. It depicts the difference in potential across two sampling capacitors(Eg: V(C2) - V(C3)).
The first...
Hi,
I am designing an 10 Bit Pipeline ADC. The power can be scaled down by scaling the unit capacitance in each stage. The major limiting factors in choosing the unit capacitance are;
1. Thermal Noise
2. Yield ( Mismatch between capacitors in IC with respect to area)
I have considered the...
Hi,
I am designing an 10 Bit 200 MSPS Pipeline ADC in TSMC 65nm process.
Just finished the design of first stage Opamp. It uses the "Folded Cascode Gain Boosted Opamp" architecture. The supply voltage is 3.3V. The total current drawn from the supply is around 90mA. Therefore, the first stage...
Good work!!!
@manikantaxyz - Thanks for providing the detailed instruction.
Hoping for successful installation.
By the way, can anybody tell the packages included in this installation.
Thanks,
Jebas.
Hi,
I got into a strange doubt while doing signal conditioning at the input of ADC. The Signal to Noise ratio is defined as the ratio of average signal power to the average noise power.
SNR = Psignal/Pnoise ; Where P is average power
(or)
SNR = (Asignal/Anoise)^2 ; Where A is rms value
Let us...
Re: Selection of resistor& Capacitor in ESD protection circuit - IEC61000-4-2 standar
Thanks GUMY, emresel & chuckey.
The suggestions are very much useful for me.
I want to share the following link from where I got more information about selecting a appropriate component for ESD protection...
Selection of resistor& Capacitor in ESD protection circuit - IEC61000-4-2 standard
Hi,
I am designing a Data acquisition system. The input of this system should provide ESD protection according to IEC61000-4-2 standard. My input section is as shown in figure. I am not afford to use...
Hi,
I am designing a DAS system which needs a board level precision of 14 bits. So, I have decided that it is better to go with 16bit precision in component level.
Input signal frequency : 200Hz (max)
Archtecture : Differential
I need some suggestions from the experience.
For argument we...
Hi,
Please confirm one thing. What is the switching frequency of the MOSFET or the pulse width.
Capacitance value depends on the switching frequency or pulse width.
yassin.kraouch, Why are u doing DC analysis here. It is a switching circuit. the capacitance is called as "De-Coupling...
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