Factors deciding Unit capacitors in Pipeline ADC

[jebaspaul]

Hi,


I am designing an 10 Bit Pipeline ADC. The power can be scaled down by scaling the unit capacitance in each stage. The major limiting factors in choosing the unit capacitance are;

1. Thermal Noise
2. Yield ( Mismatch between capacitors in IC with respect to area)

I have considered the thermal noise factor in my design. Yet to think about the "yield" factor dependency on limiting the unit capacitance. Please anyone suggest or give a pointer where can I get enough information about this. I am not looking for the exact value which is only available with Foundry. I need an approximate estimation of this mismatch to calculate the unit capacitance value.


Thanks,
Jebas.

 

[erikl]

... I need an approximate estimation of this mismatch to calculate the unit capacitance value.

Mismatch parameters depend on process size. If you can't get them from your foundry, try these approximate values from this thread.