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Recent content by jayant

  1. J

    differences in verification languages

    this does not give overview of which features are supported in some language and missing in other.
  2. J

    differences in verification languages

    what is the difference between e , vera, systemc & systemVerilog languages...please explain
  3. J

    Power Estimation for an Implimantation?

    you can use power theater or power compiler
  4. J

    difference b/w coding in vera and verilog

    since vera is meant for verification you get more flexibility to verify rtl.
  5. J

    Ideas for speech recognition final year project

    Re: final yr project u can use dsp processor tms320c25 or similar & implement the program using assembly language.
  6. J

    Looking for newbie resources about PSL

    Re: psl guide links book example zip file is password protected. Please let me know the password?
  7. J

    Looking for newbie resources about PSL

    Re: psl guide links can download from http://www.eda.org/vfv/docs/PSL-v1.1.pdf
  8. J

    Looking for a job in ASIC Verification field in the USA

    Job in ASIC Verification Does anyone have consultant addresses or contact info to apply for jobs in US. thanx
  9. J

    Looking for tutorial on cve library for SystemC

    tutorial on cve library I need good tutorial on cve library for systemC
  10. J

    about formal verification

    using formality for formal verification can flag errors when you convet ur design from one stag to another say from rtl to netlist. you can easily find out any problems occured during coversion.
  11. J

    How to begin learning specman and e language ?

    specman e lrm best way would be to start with the sbt 10 labs which are available with specman installation.
  12. J

    What is the best way to reduce power for low power ASIC?

    Re: LOW POWER ASIC you can use tool called power theater. using this you can analyze your rtl code to optimise for power at different stages.
  13. J

    gate count of design calulation

    gate count area I am using umc technology library for synthesis how can I calculate the gate count of my design if I know the cell count. moved here from DSP by davorin What the hell it has to do with DSP???? Post in right section next time or you'll risk to get warning!!
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