differences in verification languages

[jayant]

what is the difference between e , vera, systemc & systemVerilog languages...please explain

 

[AlexWan]

Maybe the following is a refer:

verilog+pli         vera                e                     systemc        system-verilog
easy                  easy               hard                hard               easy
event base        cycle base     cycle base      cycle base     event base
co-simulation    co-simulation   co-simulation  co-simulation co-simulation
need pli to         can control      can control     can control     may control <--(control memory)
no class            class               class              class              class
slow                   quick              quick              quick               slow
no assert           assert             assert           no                    assert
IEEE                  synopsys       cadence         IEEE               synopsys/Cadence
random limit       random          random            random          random

 

[jayant]

this does not give overview of which features are supported in some language and missing in other.

 

[AlexWan]

If you want to know about what features is supported by one language, you should check the introduction chapter of User Guide of each language.