What is the best way to reduce power for low power ASIC?

[jayakumarjay]

LOW POWER ASIC

Does anyone working on low power,

If yes which is the best way to reduce power


is by doing architectural analysis or gate level analysis

 

[etherios]

Re: LOW POWER ASIC

generally the higher the level of abstraction the better ste savings in power

 

[AlexWan]

LOW POWER ASIC

In some synthesis tools, there are some options for low power.
And you can get some papers from SNUG.

Good Luck

 

[negreponte]

Re: LOW POWER ASIC

Low Power design can applied in all levels of design.
The architectural design has more power savings than gate level.
Low power is a very difficult issue, you need tools like PowerCompiler Synopsis but you have to pay a lot.

 

[jayant]

Re: LOW POWER ASIC

you can use tool called power theater. using this you can analyze your rtl code to optimise for power at different stages.

 

[sudhirtj]

Re: LOW POWER ASIC

It is a combination of architectural and gatelevel design. Clock Gatings, use of low power libraries are some of the schemes used in architectural and gatelevel implementations.

 

[negreponte]

Re: LOW POWER ASIC

a good survey for low power techniques

 

[aravind]

Re: LOW POWER ASIC

a low power eda tools
it covers all eda tools in terms of low power ASIC implementation
this article will help for all research doing low power design

 

[galant]

Re: LOW POWER ASIC

In my opinion , the system level architecture design is more important than the EDA tools. Most of eda companies are always boosting their products .

 

[linuxluo]

Re: LOW POWER ASIC

hi,
first , the higher abstract level, the more power you saved.
second, use design power or power threater to help you save power.
third, custom layout

 

[kelvin_sg]

Re: LOW POWER ASIC

Agree! That's why the gov tax the rich.

To reduce power, you can use Power Compiler which does a decent job
at gatelevel optimization.

generally the higher the level of abstraction the better ste savings in power

 

[ecijun]

LOW POWER ASIC

system level is very important

 

[seanwu]

LOW POWER ASIC

Remember to reduce signal toggle, especially heavy loaded signal.
Then let EDA tools to generate a gated_clocked gate-level netlist.

 

[pradeep_dft]

LOW POWER ASIC

Low power design techniques involves (1) reducing active power (2) reducing leakage power. The former depends on architurural analysis and the later depends on gate level (even layout).

 

[AlexWan]

Re: LOW POWER ASIC

first , the higher abstract level, the more power you saved.
second, use design power or power threater to help you save power.
third, custom layout

Fourth, low power cell/lib from foundry.

 

[tony_taoyh]

Re: LOW POWER ASIC

What I think:
(1) During RTL design, add some logic to turn off some un-useful
logic under a certain mode;

(2) During synthesis, using some tools like power compiler;

(3) For the new feature, can use multiple voltage and multiple Vth.

 

[hypend]

Re: LOW POWER ASIC

make abstract level higher and use design power tools

 

[don_quixote]

Re: LOW POWER ASIC

For dynamic power, the most immediate approach is to reduce the clock freuqency and supply voltage, although it may sounds obivious. That says, as far as power is concerned, deep pipelining can really burn out your chip. I think that's why Intel has given up their Jahwak (??) project due to unresolvable power dissipation issue. Just think that Intel has been pushing the clock frequency for so many years!

For static power, leakage power is the biggest problem, especially for portable applications. Your cell phone keeps on draining power even it's on standby mode! The common techniques to address leakage power is to embed high-th transistors on critical paths while low v-th transistor on non-critical paths (so called multi-threshold), or use sleep transistors to control the leakage. There're numerous papers talking about these.

As to the original question, I think designers focuses more on architectural level while gate level analysis is pretty much handled by EDA guys and the tools they made.

 

[visualart]

LOW POWER ASIC

the Prime POwer is a powerful analyze tool

 

[linuxluo]

Re: LOW POWER ASIC

hi,
if using eda tools to do power estimation, it's better to use primepower/jupiterxt/astrorail to keep consistence. And if you have voltage storm , it's a signoff tool for 90nm and below