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Recent content by jas_bakshi

  1. J

    ADVICE ME for a cheap ALTERA STRATIX BOARD

    hi U can go for PCI development board provided by altera,which has EP1S25F1020C5 FPGA embedded overit. Bye
  2. J

    what does reg [((8*20)-1) :0] clocklab[0:28]; means ?

    This is a memory with depth of 29 and width of 160 bits.width wise bits are located as 0th bit LSB and depth wise locations are located as 28th location being the lower most.
  3. J

    what is one hot,zero one hot,zero one cold ?

    hot zero hi one hot is : 0001 0010 0100 1000 zero one hot : 0000 0001 0010 0100 zero one cold : 1111 1110 1101 1011 0111 these encoding styles use as many number of F/F's as many states we are using which is there main drawback.
  4. J

    some free downloadable system C simulator

    Hi Can anyone guide me about free downloadable System C simulator? Regards Jas
  5. J

    What to consider when writing VHDL codes for Altera devices?

    Re: Synthesis using altera Hi Nidhi I think u can use "One Hot Encoding" in ur state machines, it can optimize the synthesis results. Regards Jaspreet Singh
  6. J

    Quartus VHDL file order...

    Hi Dear I did it myself successfully in many projects.So u can take my wods. Regards Jas
  7. J

    Quartus VHDL file order...

    Hi Davolin In Qu@rtus u only have to keep Topmost entity(or module) at the bottom while adding project files.Other files can be in any order. Regards Jas
  8. J

    Who is the most demanding and challenging Engineer!!!???

    HI Its a question which can not be solved by a debatem, rather we can say that ur way of working is more demanding and challenging than ur skill set. Regards Jas
  9. J

    Statement unreachable (Branch condition impossible to meet)

    branch condition impossible to meet Hi This condition may occur when u are trying to jump from one state to other but simultaneously two next states are getting generated.Say checking same conditions for two next states.So u should check the state transition logic in your code. Regards Jas
  10. J

    Consider a 2:1 mux , what will output if sel is"x"

    mux +select (sel) is x Hi Try using casex construct,as it can resolve the contention(x) input to ur system. Regards
  11. J

    problem with NIOS II IDE.

    Hi all While using Nios II IDE, it is generating the following error : Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: OK Please tell me the probable reason for the same.
  12. J

    how to speedup quartus place & route function?

    Hi there In settings there is one option for incremental place and route.Try using that after u make minor modifications. Command line compilation using quartus_fit is another good option.
  13. J

    VLSI Front end and backend tools ?

    mentor graphics front end tools Hi The frontend is writing RTL , linting and Verifying the RTL using testbenches and testcases. Synthesis aids as an interface for frontend and backend. Backend encompases ur static timing analysis,floorplanning,clock tree synthesis, layout,signal integrity...
  14. J

    One question of VHDL simulation

    AFTER : It is used to delay the assignment of a signal like y <= x after 5ns; WAIT : wait is used to suspend a process for a finite time , it is used in the absence of sensitivity list. wait for 10 ns; Added after 56 seconds: AFTER : It is used to...
  15. J

    General questions in the field of digital design

    Re: some digital Q? ans it thanks Mr. spauls for correcting me.Ur support will be appreciated in the future.
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