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I have to get ready with the following for a job interview... can someone help me?
1. Skills to be able to create a C compiler for Finisar custom microcontroller architecture.
2. Port GCC over or build a backend to LLVM; however open to other solutions.
3. Knowledge and experience with...
Hello,
I want to know what is the system design tools/ techniques are involved in designing ETHERNET SWITCHES. It would be helpful to prepare for an interview.
Hi,
I've synthesised individual modules in a microprocessor design. (with individual verilog modules.. like for alu, memory, etc.) All were working fine; in fact each of them were synthesised within a span of 60 seconds.
But, when I put it together it doesn't happen fast. I've run the software...
hello.. can you help on this.... I have a similar problem i think..
I have created a memory design (in cadence virtuoso). I want to attach this memory with a auto generated layout - a microprocessor (generated using soc Encounter).
the plan i have in mind is..
create a blackbox LEF Macro and...
I have created a memory design (in cadence virtuoso). I want to attach this memory with a auto generated layout - a microprocessor (generated using soc Encounter).
the plan i have in mind is..
create a blackbox LEF Macro and a timing model (liberty file) for the memory design. The LEF macro...
Hello,
can you tell me how to generate those .lib files and .lef files? what do you mean by "CDs for the celtic view"?
I am actually a beginner. CAn you please give a brief info on what CDs/celtic views are ?
Thank you
---------- Post added at 15:44 ---------- Previous post was at 15:15...
Hello,
I am going to do a custom designed - register file structure in freePDK45nm library. I want to add this as a single "cell" to the freePDK45nm standard cell library so that I can use this cell for doing a microprocessor design.
CAn someone tell me how to add an extra cell to the standard...
Thanks for your reply. I think these are great inputs anyone can get and this stuff is exactly what we look for in the forums!! I will learn all those things that you said and look for a good project to do! I plan to do it this summer. thanks man for your help.
I did Electronics and Communication engineering in my undergrad. I also did work with Microcontrollers and ZigBee radios in the final project in undergrad. It was an amazing experience. I programmed the microcontroller to send the amount of "pressure" maintained in an air compressor via ZigBee...
Hello,
I am a Masters student. currently doing VLSI. I have taken courses like Analog circuits, Analog integrated circuit layout, Advanced VLSI design, Computer Architecture, RF/Microwave Circuits.
I have worked on FPGA programming, Know C, C++, Verilog well, I recently enjoyed doing the...
Hello,
Before the system crashes, I see the register files as a single block in the gui window - and the status bar in the gui window shows "computing design", etc. there's no warning/error message shown in the console window.
the console window shows "reading the varaible mem / reg [0:32]"...
Hello,
I have a problem in synthesising register files. I'm using cadence rtl compiler.
I tried to synthesise a simple 32 byte register file.
The software gets crashed/hanged. I want to know if the library FreePDK45 supports memory cells/register files.
Can anyone tell me why this happens? Is...
I'm using cadence rtl compiler and soc encounter for pnr.
I can import the layout of microprocessor to cadence virtuoso. I have the layout/extracted views of register file in virtuoso. what should i do to integrate them?
Hello,
I want to integrate full custom design - register file layout (memory structures) with the semi-custom designed microprocessor.
I have the layout files for both register files and microprocessor seperately. But I want to put the register file layout in to the microprocessor layout. Can...
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