jaishankar
Junior Member level 2
I have created a memory design (in cadence virtuoso). I want to attach this memory with a auto generated layout - a microprocessor (generated using soc Encounter).
the plan i have in mind is..
create a blackbox LEF Macro and a timing model (liberty file) for the memory design. The LEF macro defines the physical boundary and pins of the memory. I can then import the LEF and lib file into SoC Encounter along with the netlist for the micro and run P&R. This allows to create an integrated layout and verify timing between the micro and the memory
Can someone tell me how to do this?
1. how to create a black box in soc encounter? what do i need for that? how to create .lef and .lib files for my memory design??
any suggestions/ideas are welcome..
the plan i have in mind is..
create a blackbox LEF Macro and a timing model (liberty file) for the memory design. The LEF macro defines the physical boundary and pins of the memory. I can then import the LEF and lib file into SoC Encounter along with the netlist for the micro and run P&R. This allows to create an integrated layout and verify timing between the micro and the memory
Can someone tell me how to do this?
1. how to create a black box in soc encounter? what do i need for that? how to create .lef and .lib files for my memory design??
any suggestions/ideas are welcome..
