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Recent content by jagadeesh2k1

  1. J

    Semicon360 proudly announces great opportunity to step into Semiconductor Industry

    Hi, Semicon360 proudly announces great opportunity to step into the semiconductor Industry. We are seeking dynamic freshers, BE, MTech students in VLSI/Electronics/Microelctronics background. Only one opening where the selected candidate will be given training and will be working at...
  2. J

    What is the use of NT_N layer in TSMCN90_RF

    Can any one you help me why NT_N layer are used for the RF signals.
  3. J

    Shielding clock signals

    is influence of neighboring nets in the layout will affect the performance of clock signal.
  4. J

    Shielding clock signals

    shielding of signals Is is mandatory to shield clock signals.
  5. J

    What is Fringe capacitance in Layout

    Is it between different layers or between met1 and met1.
  6. J

    What is Fringe capacitance in Layout

    Can u explain what is Lateral capacitance
  7. J

    Why LVS is showing that two nets are shorted while they are not?

    In LVS it is showing two nets are shorted but actually It is not. Can any one explain the reason for the short.
  8. J

    What is Fringe capacitance in Layout

    Can any one of u explain what is fringe capacitance in layout?
  9. J

    Installation fails after 100 sec...........

    Initial installation of cad product itself fails. I have a doubt whether redhat linux supports that or not. I didn't get any error message..............I tried with the Install scape. Istallation sucessfully started it shows 36000 sec left but as soon as it reached 100 sec installation...
  10. J

    Installation fails after 100 sec...........

    My installation of cad product(virtuoso layout editor) fails after 100 sec I have redhat linux.
  11. J

    When should I use Dummy Transistors?

    transistor for dummy Dummy poly alone is enough no need for the dummy transistor.
  12. J

    How guard ring reduces parasitic resistances

    Can any one of u help me in this case of how latchup be prevented by a guard ring..........................thanks in advance
  13. J

    Metal on Poly or diffusion

    There is a practice where metal1 will be palced parellel to the gate inorder to reduce the resistance of the gate. Make sure that different signal line should not be routed over active poly region.
  14. J

    Need help in RF layout

    What are the special considerations should be taken care for RF layout.......
  15. J

    Metal on Poly or diffusion

    metal over poly mos vt Metal 1 is the immediate layer after the poly and if metal 1 carries a huge current there may be a chance of inducing electrons on the active poly which will alter the characteristics of that device........................

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