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Recent content by indu15

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    [SOLVED] solar Li-Ion battery charger

    Both the datasheets are on TI website. I have decided to use BQ24210 for my application.
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    [SOLVED] solar Li-Ion battery charger

    I am building a system that has solar panel source to supply the portable device while charging the Li-Ion battery. The solar panel 9v, 660mA is used to charge the Li-Ion battery 3.7v, 4400 mAh and the portable device of 3.3v, 500mA. While looking for Li-Ion battery charger I found these...
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    Mathworks xPC Target CAN drivers for MPC555

    I am newbie to Matlab. I have MPC555 on my board and I want to communicate with CAN devices using Mathworks xPC Target. Can anyone please let me know if there are CAN drivers available for MPC555? How much will it cost?
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    VHDL sequence detector

    Thanks TrickyDicky for the reply. Can you please let me know what do you mean by "You may want to register clk_enable_0_5mhz and align it with your edge detect"?? Can I align the sync_detect with the data in (din) signal???
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    VHDL sequence detector

    This is not a job interview question. It is a part of the code for the project I am working on. Sorry, I was not clear with my question. I have edited my question I hope this time it is clear. Please see my question again and help me to solve the problem. Thank you.
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    VHDL sequence detector

    I have generated 0.5 Mhz clock from 50Mhz incoming clock by using synchronous counter clock enable and detecting the 00110001 pattern on the din input data and outputting (sync_detected) pulse once the last bit in the pattern is detected. When I implemented the code that is mentioned below I am...
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    VHDL clock divider warning

    mrfibble, I will do as you said and will work on clock enable first. Thanks for the help.
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    VHDL clock divider warning

    Thank you mrflibble. When I change the code as below. I am able to get it but with warning. WARNING:PhysDesignRules:372 - Gated clock. Clock net clk_div_OBUF is sourced by a combinatorial pin. process(clk, clk_div, rst) begin if(rst = '0') then dout <= '0'; state <= A; elsif...
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    xilinx DCM for clock divider

    Yes, you are correct mrfibble. I am new to vhdl. Do you think I need to use clock enable to get both the desired clocks (1.5 MHz and 0.5 Mhz)?
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    VHDL clock divider warning

    Here is my code and errors I am getting. clk_div is dividing the clk by 3 and at the rising edge of the clk_div I need to detect the 00110001 pattern on the incoming din and output the sync pulse. Please help me with it. Thank you. ENTITY sync IS PORT ( clk : IN std_logic; rst : IN...
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    xilinx DCM for clock divider

    I need to divide the 50 MHz clock to 1.5 Mhz and 0.5MHz both with with 50% duty cycle. For this I want to use Xilinx DCM. To get 0.5MHz (2 us) from 50Mhz (20 ns) I need to divide input clock by 100 but DCM can divide only till 16. To get 1.5 Mhz (0.66666 us) from 50Mhz (20 ns) I need to...
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    VHDL clock divider warning

    When I modified my code as for K-J suggestion I am getting error - Sequential logic for node <state> appears to be controlled by multiple clocks.
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    VHDL clock divider warning

    I want to divide the clock by 3 with 50% duty cycle (see below for my code). The code is synthesized successfully but when running implement design (in Xilinx ISE) I am getting following warning. I think I cannot ignore these warnings. I am a newbie to VHDL. Can anyone please tell me what...
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    VHDL clock divider warning

    I have to divide the clock by 3 with 50% duty cycle (see below for my code). The code is synthesized successfully but when running implement design (in Xilinx ISE) I am getting following warning. I think I cannot ignore these warnings. I am a newbie to VHDL. Can anyone please tell me what...
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    VHDL eliminate delay

    Actually, in my code the process1 contains the sequence detector i.e. when the sequence is detected then the pulse is generated which is assigned to 'a' and in process2 when there is rising_edge(clk) and sequence is detected then c <= d. I cannot enable c with b since b is sequence detector code...

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