VHDL clock divider warning

[indu15]

I have to divide the clock by 3 with 50% duty cycle (see below for my code). The code is synthesized successfully but when running implement design (in Xilinx ISE) I am getting following warning. I think I cannot ignore these warnings. I am a newbie to VHDL. Can anyone please tell me what changes do I need to make in my code to avoid these warning?


WARNINGhysDesignRules:372 - Gated clock. Clock net clk_div_OBUF is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:Route:455 - CLK Net:clk_div_OBUF may have excessive skew because



code:

process (clk, rst)
begin
if (rst = '0') then
pos_cnt <= (others=>'0');
elsif (rising_edge(clk)) then
if (pos_cnt = "10") then
pos_cnt <= (others => '0');
else
pos_cnt <= pos_cnt + '1';
end if;
end if;
end process;

process (clk, rst)
begin
if (rst = '0') then
neg_cnt <= (others=>'0');
elsif (falling_edge(clk)) then
if (neg_cnt = "10") then
neg_cnt <= (others => '0');
else
neg_cnt <= neg_cnt + '1';
end if;
end if;
end process;

clk_div <= '1' when ((pos_cnt /= "10") and (neg_cnt /= "10")) else -- /= is not equal operator
'0';

 

[amitjagtap]

Now you ignore the warning.......after implement place n route ....check implement and place-route report....whether this particular net is routed or not.....Generallly tool will route these kind of nets in place n route even though it is showing warning in implement stage...
Best of Luck....
HOpe it is helpful to you....

 

[TrickyDicky]

This is bad advice. Clkdiv is clearly being used as a click elsewhere in the design, which is bad idea on an fpga

 

[K-J]

I have to divide the clock by 3 with 50% duty cycle (see below for my code). The code is synthesized successfully but when running implement design (in Xilinx ISE) I am getting following warning. I think I cannot ignore these warnings. I am a newbie to VHDL. Can anyone please tell me what changes do I need to make in my code to avoid these warning?

First would to read the warning...they tell you right there what you need to do

WARNINGhysDesignRules:372 - Gated clock. Clock net clk_div_OBUF is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.

Go through your code and change this...

if rising_edge(clk_div) then
  -- Your stuff here
end if;

To this...

if rising_edge(clk) then
   if (clk_div <= '1') then
      -- Your stuff here
   end if;
end if;

Kevin Jennings

 

[indu15]

When I modified my code as for K-J suggestion I am getting error - Sequential logic for node <state> appears to be controlled by multiple clocks.

 

[mrflibble]

Then you failed to correctly apply the coding template that was suggested by K-J. Please post the new code + the new error messages so no assumptions have to be made.

 

[indu15]

Here is my code and errors I am getting. clk_div is dividing the clk by 3 and at the rising edge of the clk_div I need to detect the 00110001 pattern on the incoming din and output the sync pulse. Please help me with it. Thank you.

ENTITY sync IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
clk_div : inout std_logic;
din : IN std_logic;
dout : OUT std_logic);
END sync;

ARCHITECTURE BEHAVIORAL OF sync IS

TYPE state_type IS(A, B, C, D, E, F, G, H);
SIGNAL state : state_type := A;
signal pos_cnt :std_logic_vector (1 downto 0);
signal neg_cnt :std_logic_vector (1 downto 0);

begin

process (clk, rst)
begin
if (rst = '0') then
pos_cnt <= (others=>'0');
elsif (rising_edge(clk)) then
if (pos_cnt = "10") then
pos_cnt <= (others => '0');
else
pos_cnt <= pos_cnt + '1';
end if;
end if;
end process;

process (clk, rst)
begin
if (rst = '0') then
neg_cnt <= (others=>'0');
elsif (falling_edge(clk)) then
if (neg_cnt = "10") then
neg_cnt <= (others => '0');
else
neg_cnt <= neg_cnt + '1';
end if;
end if;
end process;

clk_div <= '1' when ((pos_cnt /= "10") and (neg_cnt /= "10")) else
'0';

--00110001 pattern detecting
process(clk, clk_div, rst)
begin
if(rst = '0') then
dout <= '0';
state <= A;
elsif (rising_edge(clk)) then
if(rising_edge(clk_div)) then
case state is
when A =>
dout <= '0';
if(din = '0') then
state <= B;
else
dout <= '0';
state <= A;
end if;

when B =>
if(din = '0') then
dout <= '0';
state <= C;
else
dout <= '0';
state <= A;
end if;

when C =>
if(din = '0') then
dout <= '0';
state <= C;
else
dout <= '0';
state <= D;
end if;

when D =>
if(din = '0') then
dout <= '0';
state <= B;
else
dout <= '0';
state <= E;
end if;

when E =>
if(din = '0') then
dout <= '0';
state <= F;
else
dout <= '0';
state <= A;
end if;

when F =>
if(din = '0') then
dout <= '0';
state <= G;
else
dout <= '0';
state <= A;
end if;

when G =>
if(din = '0') then
dout <= '0';
state <= H;
else
dout <= '0';
state <= D;
end if;

when H =>
if(din = '0') then
dout <= '0';
state <= C;
else
dout <= '1';
state <= A;
end if;
when others =>
NULL;
end case;
end if;
end if;
end process;

end BEHAVIORAL;


ERRORS :

ERROR:Xst:1534 - Sequential logic for node <state> appears to be controlled by multiple clocks.
ERROR:Xst:739 - Failed to synthesize logic for signal <state>.
ERROR:Xst:1431 - Failed to synthesize unit <sync>.

 

[mrflibble]

process(clk, clk_div, rst)
begin
if(rst = '0') then
dout <= '0';
state <= A;
elsif (rising_edge(clk)) then
if(rising_edge(clk_div)) then
case state is
when A =>
dout <= '0';
if(din = '0') then
state <= B;
else
dout <= '0';
state <= A;
end if;

Do you think this will generate a synchronous reset, or an asynchronous reset?

I have formulated a genius plan. How about you make a simple module (without the case statement mucking things up), with just a clock and a clock enable. Then write a testbench to see if you understand how the CE works. After you get that working, try and add a reset, see the difference between sync & async reset. After you get that working then plonk in the case statement again.

I know I know, that is far too systematic and will get you a result faster, but sometimes you just have to do these crazy things...

- - - Updated - - -

Additionally: holy crap. Just now I noticed the rising_edge on clk_div. Uhm, yeah. Go read up on coding templates for clock enables first. You are just making stuff up and hope the synthesizer gets it. Okay, real quick google result: http://www.asic.co.in/Index_files/verilogexamples.htm#link4

Note the lack of posedge on the clock enable signal. Because ... CE is rightfully treated as a logic signal, not a clock signal. You might want to rename clk_div to something like "ce" or "clock_enable" or "clk_enable" or whatever name conventions you like. Because it is an enable, not a divided clock. Best name it as such too.

Also note the FF with CE and async reset example: http://www.asic.co.in/Index_files/verilogexamples.htm#link5

 

[indu15]

Thank you mrflibble. When I change the code as below. I am able to get it but with warning.

WARNINGhysDesignRules:372 - Gated clock. Clock net clk_div_OBUF is sourced by
a combinatorial pin.

process(clk, clk_div, rst)
begin
if(rst = '0') then
dout <= '0';
state <= A;
elsif (rising_edge(clk_div)) then
case state is
when A =>
dout <= '0';
if(din = '0') then
state <= B;
else
dout <= '0';
state <= A;
end if;

 

[FvM]

To detect the difference between the suggested clock enable construct and the erroneous nested clocks, looking sharp might help, too.

But I basically appreciate mrflibble's suggestion.

In addition, I'm not able to read a sense into the pos_cnt/neg_cnt structure driving clk_div.

P.S.:

When I change the code as below. I am able to get it but with warning.

Now you are returning to the original code.

 

[mrflibble]

well obviously. because you do what you do, not what I said.

I have formulated a genius plan. How about you make a simple module (without the case statement mucking things up), with just a clock and a clock enable. Then write a testbench to see if you understand how the CE works. After you get that working, try and add a reset, see the difference between sync & async reset. After you get that working then plonk in the case statement again.

And you can use these as inspiration:

http://www.asic.co.in/Index_files/verilogexamples.htm#link4
http://www.asic.co.in/Index_files/verilogexamples.htm#link5


Alternatively you can read the Xilinx docs, which also state vhdl and verilog code templates for flip-flops with clock enable. But I am too lazy right now to go and check where exactly that was. Lemme get me some tea first.

 

[indu15]

mrfibble, I will do as you said and will work on clock enable first. Thanks for the help.

 

[mrflibble]

Progress!

Also, after you synthesize the design you can check the result in ISE with "View RTL Schematic" and "View Technology Schematic". That can really help in understanding how your code affects the exact synthesized results.