VHDL eliminate delay

[indu15]

VHDL clock delay problem

I have 2 processes in my code for example as shown below. If I run the simulation c output is taking place with 1 clock period delay after a = '1'. Can anyone please help me to get the c output when a = '1' without delay?

begin
process1: process(clk)
if rising_edge(clk) then
a <= b;
end process process1;

process2: process(clk, a)
if rising_edge(clk) then
if (a = '1') then
c <= d;
end process process2;

end;

Thanks a lot!

 

[TrickyDicky]

Make c enabled with b rather than a.

 

[indu15]

Actually, in my code the process1 contains the sequence detector i.e. when the sequence is detected then the pulse is generated which is assigned to 'a' and in process2 when there is rising_edge(clk) and sequence is detected then c <= d. I cannot enable c with b since b is sequence detector code its not one value.

 

[TrickyDicky]

If your setting a to 1 when sequence detected, why not just enable c on sequence detect instead?

 

[FvM]

VHDL is a hardware description language, it's helpful to imagine the 2 flip-flop circuit described/modelled by the VHDL program in post #1. You'll understand why it must behave as it does. If you don't like the behaviour, design a different circuit.

Generally speaking, we can't suggest a different circuit with knowing the exact problem. We e.g. don't know if the actions specified in both processes must be clock synchronous.

Sketch a hardware circuit or a timing diagram or specify the intended behaviour otherwise.