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I have generated 0.5 Mhz clock from 50Mhz incoming clock by using synchronous counter clock enable and detecting the 00110001 pattern on the din input data and outputting (sync_detected) pulse once the last bit in the pattern is detected. When I implemented the code that is mentioned below I am able to generate the waveform in the image (I have zoomed in so that you can see the problem that I am facing). My problem is that sync_detected is generated at the falling edge of the clk_enable_0_5mhz but I want to have sync_detected at the rising edge of the clk_enable_0_5mhz i.e. at the same time as the last bit in the pattern is detected. Please check my code below and let me know where I am going wrong. I really appreciate your help. Thank you.
constant PATTERN_TO_DETECT : std_logic_vector(7 downto 0) := "00110001"; signal decoder_shift8 : std_logic_vector(7 downto 0); signal temp1 : unsigned(6 downto 0); begin ----Generating 0.5Mhz clock from 50Mhz global clock pattern_detector_clk_0_5mhz : process(clk_50mhz) begin if clk_50mhz'event and clk_50mhz = '1' then if rst = '0' then clk_enable_0_5mhz <= '0'; temp1 <= (others => '0'); else temp1 <= temp1 +"1"; clk_enable_0_5mhz <= '0'; if temp1 >= x"63" then --hexadecimal value for 99 temp1 <= (others => '0'); clk_enable_0_5mhz <= not clk_enable_0_5mhz; end if; end if; end if; end process; --00110001 pattern detecting by using shift register decoder_shift_reg_proc: process (clk_50mhz) begin if clk_50mhz'event and clk_50mhz = '1' then if rst = '0' then decoder_shift8 <= (others => '0'); elsif clk_enable_0_5mhz = '1' then for i in 0 to 6 loop decoder_shift8(i+1) <= decoder_shift8(i); end loop; decoder_shift8(0) <= din; end if; end if; end process; sync_detector_process: process(decoder_shift8) begin if decoder_shift8 = PATTERN_TO_DETECT or decoder_shift8 = not PATTERN_TO_DETECT then sync_detected <= '1'; else sync_detected <= '0'; end if; end process; end;