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I begin to learn about RF not long before, by reading few books,RF Ciruit Design Theory and Application(Reinhold Ludwig),RF microelectronics(Razavi) and microwave engineer. I should i do now except reading the three handbooks, some more? Are there some forum or website about the RF ? Should i...
Hey, everybody in the forum. I'm want some suggestions in the choice of university for further study.
Now , I am a student from UESTC (university of electronics science and technology of China) and I will receive my Master degree three years later ,then I'll apply for further study in the field...
Many thanks for your help.
Now,I guess the current outstrip its maxim value . Any transistor has a limited load capacity. The value equals to output voltage Ve
divided by maxim output current . So when the load smaller than the minimum as mentioned , we can see what have happened.
when the emitter follower overload, the output get truncated
In a design of emitter follower, when Rl get smaller to less 1k, the output Vo is truncated.
The schematic as follow:
The simulation result of Pspice as follow:
As I know , in a emitter follower , Vb is fixed according to...
I design a very simply transistor circuit, and we all know about it.
The frequency of input signal is 1KHZ ,and magtitude is 1Vp-p.when the load resistor Rl5=100K， the Pspice give me such a result as below:
在输入为1KHZ，1Vp-p情况下，在100KHZ负载情况下该电路的仿真效果图：
**broken link removed**
Obviously ,the output...
//version1.1
//使用标准库函数void *memchr(const void *str, int c, size_t n);
#include<stdio.h>
#include<string.h>
#define LEN 80 //maximum of your string
int main()
{
char string[LEN];
char ch;
char * addr;
printf("please enter a string:\n");
while(gets(string)&&string[0]!='\0')
{...
Long time since last login.
I have to say the data flow from CIC to HB ,then to FIR have been such a nightmare for me.
i use the CIC .HB and FIR filter in my project of DDC.
the sampling data go through mixer,the to the three filter above.
the word length to cic is 20bits, output data is 20...
Thanks a lot.
The signal 'nd' appeared when i change the configuration from nonsymmetric to symmtric.
but the rfd_fir are set,,that means it wait for a data input. but at this moment the rdy_cic isn't necessarily set as a result of dfferent latency, so the data to fir may be invalid. That's why...
Many thanks for your help.
The signal mention above is used to make a connection between two component in my project , cic_filter and hb_filter.
To some reason i have to store the result of cic filter and then, wait until it's request by the hb filter.
For the first time ,i used two register...
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