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Recent content by hfooo1

  1. H

    two test clock in ATE test

    plz give a demonstration on the circuit using two test clock at DFT mode. thanks
  2. H

    two source clock in DFT mode

    thank you for your reply. but i mean using both two clocks in one chain. i ask for the detail.
  3. H

    two source clock in DFT mode

    can you explain why to adopt two source clock and how? i only heard about this,and not suffer such situation.
  4. H

    How to define an internal clock in DC?

    the two clocks work coinstantaneously or not? in either situation i dont think it's needed to define a clock.
  5. H

    Routing of special net (analog) Encounter

    draw them manually and set donttouch
  6. H

    When we run power separation check?

    Re: Power Separation Check what is it? plz explain it. thanks
  7. H

    What are the factors that determine the setup time of a flip-flop?

    Flop setup time you can check std.lib look for the factor in the lookuptable
  8. H

    How to solve congestion problem after CTS without effecting skew and timing?

    congestion how do u optimize the skew? CTO?
  9. H

    Do we have to meet skew limit ?

    skew i think thereis no problems but u may analyse skew VIOs
  10. H

    cell_rise(fall) rise_transition(fall)

    cell_fall rise_transition thanks a lot ! very clear! Added after 1 hours 52 minutes: if those threshold in std.lib are set different from those of ram.lib and PLL.lib what should i do?
  11. H

    Clock Tree Synthesis and RTL synthesis

    Re: Clock Tree Synthesis maybe differernt flow
  12. H

    How to do fishbone and H-tree ?

    please explain how to do fishbone and H-tree , and advantage (disadvantage) of them. thanks in advance
  13. H

    Which cell delay to use when calculating data arrival time?

    AND (A , B , .Y(n1)); DFF (.D(n1) , CK , Q ); when we calculate data arriving time, whick cell delay should we use , path delay from A to Y or B to Y? how does tool think about it ?
  14. H

    In what situation Design Compiler will synthesis RTL into latch?

    in waht situation Design Compiler will synthesis RTL into latch? someone said we dont use latch because of DFT problem. But can we solve it by adding a MUX before it?
  15. H

    cell_rise(fall) rise_transition(fall)

    rise_transition info of BUF in slow.lib: pin(Y) { timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_7x7) rise_transition(delay_template_7x7) cell_fall(delay_template_7x7) fall_transition(delay_template_7x7)...
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