Do we have to meet skew limit ?

[designer_ec]

Hi,
If design having good timing i.e design meet setup and hold,but skew is not meeting as per skew limit.Is it problem for design? or we need to meet skew contrain also.If not meet skew limit ,what will be the problem.

 

[hfooo1]

skew

i think thereis no problems
but u may analyse skew VIOs

 

[MarcS]

Re: skew

There is no problem. Skew is a means to an end, not an end in itself. If all you setup and hold times are OK, then everything is fine.

That said, many layout teams insist on achieving the specified skew target because they believe it makes the circuit more robust against variations.

 

[ushisna]

Re: skew

What I feel is set up and hold time parameters have a dependency on skew value also.Skew changes will affect the set up and hold time.Youe have said there is no violation of hold and set up time requirements which implies that skew value is not causing any problem.
But the marginality skew needs to be taken in to account,I feel so.:|

 

[apallix]

Re: skew

Skew is ABSOLUTELY critical. Lets say you have a hold margin of 50ps in a flop-flop path and the skew is >50ps, then your circuit will definitely fail at any frequency.

Added after 2 minutes:

in my above example, I am assuming that the hold margin is measured assuming an ideal clock network which is typically the case.

 

[MarcS]

Re: skew

Apallix, you should read designer_ec's original question carefully. He states that the circuit timing works and all setup and hold times are met.

You are confusing local skew with global skew, and you are also confusing a skew limit with actual skew.

Let us say, to take your example, that you design your circuit with a skew margin of 50ps. This does not mean that every flop-to-flop delay is at the critical edge of meeting timing (slack = 0). There are many many flop-to-flop delays that have plenty of positive slack, so they can tolerate a lot of local (adjacent flop) skew and still work.

It is typically only the critical path that has zero slack, and there you want the skew from one flip-flop to the next to be less than 50ps, but the global skew can be much bigger.

The global skew measures the difference between the earliest and the latest arrival times at any flop in the clock - even if there is never a signal that goes between them!

So you can easily violate your global skew limit and still have a circuit that works perfectly well. Think about it.

 

[apallix]

Re: skew

Hi MarcS, I agree with you reg local skew and global skew. But one question is, does STA include clock skew when it measures hold and setup margins? My experience as a custom circuit designer is that STA assumes that all clocks are ideal with no skew when it measures setup and hold margins and skew(local or global) is calculated by a separate flow and is expected to meet its limits.

 

[jarodz]

skew

Hi apallix,
The STA tool will analysis clock delay(the true clock tress) when you use "set_propagated_clock"(primetime) at post_CTS stage.

Sincerely,
Jarod

 

[MarcS]

Re: skew

Hi apallix:

STA can be run before the clock network has been created (= ideal clock) or after the clock network has been inserted (= propagated clock).

In ideal mode, you are correct that the clock is assumed to arrive everywhere with zero skew, but the SDC constraints do build in a margin for clock skew called the clock uncertainty. So the amount of time available for a signal to go from the launching FF to the capturing FF is = Clk_period - setup time - clk_uncertainty.

In propagated mode, however, all the clock arrival times at every FF can be calculated exactly and there are no assumptions made about skew. The timing equation (for setup) becomes:

Clk_period >= Datapath_delay + Setup + Capture_clock_insertion_delay - Launch_clock_insertion_delay

Notice how there are no estimates or limits here - every delay can be exactly computed. If the equation (and the similar one for hold) is satisfied then the timing works, no matter what the skew is.