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Hi All,
There is a multi if statement in licensed IP, which is like :
reg [width-1:0] array [depth-1:0];
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
reset process
end
else begin
if(condition A) array[index1] <= variable1;
if(condition B) array[index2] <=...
Hello everybody,
I am trying to synthesis a big IP with bottom up flow.
the ratio of registers which are clock gated in the report of each sub-blocks is very high ,such as around 85%.
When I synthesize TOP module, I use netlist of previous sub-blocks and don't turn on the "dont_touch"(want some...
I read some OCP docs, Actually I think OCP is just a kind of bus protocol as others like AMBA.
according to OCP-IP answers, ocp is described as a socket.
thanks & merry chiristmas!!!
1:
What is the difference between the OCP and standard bus specifications?
A:
There are fundamental...
Formality help!
Hi all,
I met a strange issue when I do formal check for RTL vs. Netlist.
In RTL :
reg [31:0] FIFO [ 3:0];
reg[2:0] Wptr;
always @ (posedge)
if(push)
FIFO[Wptr] = Din[31:0];
FIFO depth is 4, but the Wptr is defined 0~7
I found that FIFO[0] ,FIFO[1],FIFO[2],FIFO[3] are all...
hold time dbt
dazzling_deepika， in synchronous circuit, all flipflops are toggled by the same clock. at the same edge of clock, the neighbour flipflops latch their D input. if hold time is not meet, the updated data of previous flipflops will be latched by the next flipflops. that was not you...
I2c doubts
System clock is generally faster than SCL. We can use system clock to measure the width of SDA or SCL, for example ,if the width is larger then 8cycle of system clock, that means that SDA and SCL is stable and the transistion is not glitch.
ahb master bus request after split response
For example,
For AHB write transaction, if the command buffer or data buffer is full, the slave has to stop the master, so it will give split response to master. it will be good to a shared AHB bus.
Hello everybody,
Does anyone have experience or hear about wrapping DDR controller commands to access external SDR DRAM, that is, changing DDR commands to SDR type?
thanks
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