heartfree
Advanced Member level 4
Hello everybody,
I am trying to synthesis a big IP with bottom up flow.
the ratio of registers which are clock gated in the report of each sub-blocks is very high ,such as around 85%.
When I synthesize TOP module, I use netlist of previous sub-blocks and don't turn on the "dont_touch"(want some optimization between boundary of sub-blocks).
but in the final result of report_clock_gating of TOP design, the ratio is pretty low, as 13%.
do you know what's the reason?
thanks
I am trying to synthesis a big IP with bottom up flow.
the ratio of registers which are clock gated in the report of each sub-blocks is very high ,such as around 85%.
When I synthesize TOP module, I use netlist of previous sub-blocks and don't turn on the "dont_touch"(want some optimization between boundary of sub-blocks).
but in the final result of report_clock_gating of TOP design, the ratio is pretty low, as 13%.
do you know what's the reason?
thanks