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Recent content by hawk_chenbo

  1. H

    valid-ready pipeline protocol

    valid ready pipeline you can refer to AXI portocol. What's more, buffer is needed to support ready-before valid.
  2. H

    anyone has this ASIC book ??

    It is in E-book download/upload sub-forum. There are many other E-book may be useful for you. Enjoy them.
  3. H

    design of a ddr sdram controller

    Say Data from internal bus is 32-bit width, Data[15:0] can output when output clock is high and Data[31:0] when clock is low.
  4. H

    want help in System verilog.

    It is so easy. There are some examples in SV, which are attached in EDA simulatior.They are good reference.
  5. H

    Hardware/Software interface

    The binary code correpond to certain CPU intructions, which are implemented by hardware CPU.
  6. H

    Random Test Generator and Seed

    The random mechanism is pseu-random. If you are interest in the sequence of the instruction, you can research on the pseu-random mechanism.
  7. H

    what is the relations of real time to simulation time?

    I think you can take in account the time spent besides the functional simulation by "display the time at the very beginning of simulation".
  8. H

    Looking for info about using System Verilog for verification

    SYSTEM VERILOG VCS and Cadence NC-incisive have some examples for systemverilog, they are good for newbie.
  9. H

    NC verilog switching activity and power

    Your thought seem a little innovative. According to my experice, you can make a power consumption using Synopsys PrimePower.
  10. H

    How to make a SystemVerilog Class to read a text vector

    fscanf system verilog I think PERL or Python are more suited for text handling.
  11. H

    Functions of Monitor and Checker.....for any block...?

    They are based on your functional description, for example bus protocol. It is convenient to implement them in assertion language.
  12. H

    Which Tool can help my work?

    I think you only need to integrate an anolog simulation into the digital part, then run simulation same as pure digital logic.
  13. H

    any docs on USAGE of PERL language in VLSI field......

    www.perl.org is good website for learning PERL.
  14. H

    can we estimate power consumption with CAD tool

    report_power sequence Surely. For example, Synopsys Power Compiler.
  15. H

    Synthesis constraints

    synopsys set_max_transition set_max_transition: it is one of design rule, it constrains the max transition time on clock; set_clock_uncertainty: it accounts for clock skew; set_load: Sets load attribute value on specified ports and nets.
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