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Re: LEC - why RAM as "Not Translate" or as "black box", and lib file's also in LEC.
I would like to add here, it depends on the License that you use, Normally the 1 Hour is XL ind of license. (Not GXL). Am i right OhaAmo?
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1 week run time, even I have seen - when have...
But with hell lot of congestion issue in Physical design, and in many seminars I heard the same thing, that we cant think beyond 5 or 4 nm.
FinFET's or other way of workaround, we are trying with nm., not with pico.,
If any pico research kind of info you have, can you share please.
Hariharan B
Hi Guys,
Please help me., like how can we make a generic equation to skew, considering all type of clock frequencies.
Skew = x + y + z .... ?
Thanks
Hariharan GB
Thanks Yang,
Can you please comment on the below as well.
If I am starting my synthesis, and say for example I have a critical path group violating with 3ns.
I have given set_path_group -name xxx -weight < 4 >
Correct me, if my understanding is wrong.
This means worst 4 path down from WNS will...
Hi
In the synthesis command below:
DC Shell >> group_path -name <> -from <> -to <> -weight 2
what is this weight 2 represents in group path? can anyone explain exactly, what it does to our synthesis process ?
Thanks
Hariharan B
To my knowledge -
Uncertainty - the equation comprises addition of
( Jitter + Tool delta Uncertainty + skew (for prelayout) + OCV + few percent of wireload)
+++++++++++++++++++++++++++++++++++++++
Assuming we can have a 5 - 10 % of clock for Jitter.
Can anyone please tell me how this skew...
Thanks for the replies, guys :wink:
- but when we think beyond the estimate graphs, (say for example - the very famous question - "what would be next"), i hope we still not got a clue to predict further!
- Hey <tpetar> - thanks for the graph:
- But do we have something to think beyond CMOS, a...
To best of my knowledge i am sure, that we don't put a Spare FF/gates in a scan chain, until it is a spare flop/cell.
Once when it decided that we want to use this spare flops, we make ECO for both functional replace and scan replace and then finally a new ATPG vector pattern would be...
Yes i agree, that the spare cells would be some where present in a CHIP, which doesn't initially put up in a scan chain.
Once an ECO is needed and by that time, we use this spare cells, flops, and put into the scan chain as well, and regenerate vectors for ATPG.
with this i have new doubt born...
Even i thougt of asking this question, thanks for posting.
Before that what is this spare combo cells pack, what are all its composites, and where it will placed in a chip? How its composition looks like? will they fuse it when needed as in FPGA? or a combinational back present is reused? if so...
I have very silly question, but interested to get a detailed answer or analysis for all (5 "wifes") where?, when?, why?, what? Will? and (1 Husband) how? :P
Question:
1) What is propagated clock in a ASIC Clock?
2) Will the clock be called in such a way, and hence it is be termed and is it...
As we see in VLSI field, our technology has already reached 28nm, 18nm and so on.
With gate_size, range keep on decreasing, i believe one or the other day, it will freeze for sure.
Do researchers, targetting on pico level, pm technology like that (pico meter 10^-12)?
Is MEMS, goona do...
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