where to get how much clock uncertainty should be assigned

[rogeret]

In DC, when using set_clock_uncertainty to model the pre-layout clock tree , where can i get the info how much clock uncertainty should be assigned?
thanks !

 

[hariharan.gb]

https://www.altera.com/literature/ug/ug_hc2_cuc.pdf

hope that lkink will help you some how?

if found more materials plz do share...


Hari

 

[rogeret]

thanks!
sure

---------- Post added at 13:50 ---------- Previous post was at 13:42 ----------

this link is from vendor of FPGA which is greatly different from asic for clock tree in FPGA has already been P&R. Could you plz give me a general description ?

 

[soloktanjung]

Try look at this link: https://www.edaboard.com/threads/94153/. Maybe it can helps you with something.