[SOLVED] What is Propagated Clock in ASIC flow?

[hariharan.gb]

I have very silly question, but interested to get a detailed answer or analysis for all (5 "wifes") where?, when?, why?, what? Will? and (1 Husband) how?

Question:
1) What is propagated clock in a ASIC Clock?
2) Will the clock be called in such a way, and hence it is be termed and is it like where we have a black box and when we do STA for our block, we call it as propagated clock? Is that right? please give some brief note here >>>
3) Why we do so and what is the exact reason behind that, and if i want to constraint how i will constraint it?
4) Any brief spoon feeding analysis is also welcome. (need to know completely what is it?)

Hope all 5wives and 1husband is covered...

Hariharan B

 

[pavanks]

See before the CTS (clock tree synthesis) we dont have the actual tree built. So we come up with some estimated latency value and with this we try to analyze and optimize ur design.
But once the clock tree is built then we say that the clock is propagated and now we dont require any latency value as the tool will calculate the exact latency.

Thats all the logic here nothing else.