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Hi, I have the logic that generate DDR output signal e.g.
assign DDR_out = clk ? DDR_pos_reg : DDR_neg_reg
and using DC to synthesis it. clk signal is the select of the mux and create data value on both edge. This architecture is valid as mentioned in https://www.edaboard.com/threads/257864/...
After searched internet, I found my answer for my question. My assumption is correct and it is called normal boot which compare to fast boot (max 52Mhz). Some stuff are found from SoC application manual.
Hi everyone,
I looked at the EMMC 5.1 standard from JEDEC and want to know the max data transfer rate in boot operation mode right after power on. I saw f_od max = 400Khz so data transfer rate may equal 400 * 8 * 2 = 6.4 Mb/s = 0.8 MByte/s for max configuration x8, DDR. Is my understanding and...
Yes, the daisy chain is already clocked to neg edge TCK inside the BIST logic and connect to BIST_TDO. Then I sync all other TDO (ID code, IR, Bypass) to neg edge TCK before mux all of them to TDO_out. TDO_out will be going out to TDO pad and do not connect to any internal daisy chain.
So the...
Thanks John :thumbsup:
I understood the cleaner approach you said, it is better way but I can not do it. My design have some daisy chain in BIST logic then it has its own TDO signal that is clocked to failing edge of TCK. It is fixed and I can not remove those flipflops before the MUX of TDO...
Hi everyone,
I have question about TDO signal. My design have some TDO signal from ID code, IR, Bypass and BIST. All of them are clocked to failing edge of TCK.
Then I have a MUX of all TDO into TDO_out. Do I need one more flipflop to clock the TDO_out to the failing edge of TCK before it...
The problem that I can not write a wrapper is because of the width mismatch is from some IP modules in lower hierarchy level. These module are generated by tool and I don't have permission to modify them.
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Yes. I'm searching solution around before contact with their...
Thank rca. So what dc_shell command that i can use to control it?
Because right now, my DC synthesis script can run but it return a gate netlist with blackbox and it is absolutely a wrong netlist. All my functional logic is affected by this error.
PS: Talus can synthesis normally and it return...
Hi all,
I have trouble with dc_shell. My design contain some small RTL module which are generated by EDA tool. They contain some connections that have mismatch between port size and connection size but do not affect to functional logic. I tested my design with QuestaSim, VCS and synthesis by...
Hi everybody,
I have synthesized my rtl code with some talus command but it has error message that i can't understand. Can anyone give me some advices?
Here is my talus script:
set l /stdlib
set rams /memlib
import lib -lib $l /data/projects/***.lib
run prepare lib $l
import lib -lib $rams...
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