Error when using Talus to synthesize

[haianh]

Hi everybody,

I have synthesized my rtl code with some talus command but it has error message that i can't understand. Can anyone give me some advices?

Here is my talus script:

set l /stdlib
set rams /memlib
import lib -lib $l /data/projects/***.lib
run prepare lib $l
import lib -lib $rams /data/projects/***.lib
run prepare lib $l
config rtl targetlib $l $rams

### part 1
source /data/projects/***
set design MODULE1
run rtl elaborate $design
set m /work/$design/$design
force rtl cross_boundary $m off -hier
fix rtl $m
fix netlist $m $l
config timing clock multiple on 
force timing clock $m/CLK 100p
config message level CK-347 warning
fix time $m $l -rtl -libonly
check timing $m -detail -file  ***.txt 
report timing check $m -file  ***.txt 
report timing path $m -late -number 100 -file  ***.txt 
set design SUBMODULE1_1
set m /work/$design/$design
data flatten $m
run gate sweep $m
export verilog netlist -minsize $m /data/projects/***
export volcano -compression max -object $m SUBMODULE1_1.volcano
set design SUBMODULE1_2
set m /work/$design/$design
data flatten $m
run gate sweep $m
export verilog netlist -minsize $m /data/projects/***
export volcano -compression max -object $m SUBMODULE1_2.volcano

### part 2
source /data/projects/***
set design MODULE1
run rtl elaborate $design
set m /work/$design/$design
force rtl cross_boundary $m off -hier
fix rtl $m    # i found here is the comand cause error #
fix netlist $m $l
config timing clock multiple on 
force timing clock $m/CLK 100p
config message level CK-347 warning
fix time $m $l -rtl -libonly
check timing $m -detail -file  ***.txt 
report timing check $m -file  ***.txt 
report timing path $m -late -number 100 -file  ***.txt 
set design SUBMODULE2_1
set m /work/$design/$design
data flatten $m
run gate sweep $m
export verilog netlist -minsize $m /data/projects/***
export volcano -compression max -object $m SUBMODULE2_1.volcano
set design SUBMODULE2_2
set m /work/$design/$design
data flatten $m
run gate sweep $m
export verilog netlist -minsize $m /data/projects/***
export volcano -compression max -object $m SUBMODULE2_2.volcano

exit

When talus run, it can synthesize part 1 but cant synthesize part 2. MODULE1 and MODULE2 exactly are the same module, they are only different by instance name and in/out port name.

Talus logfile for part 1:

################### Starting Standard fix rtl ####################

ENW-160 Initializing snap system...
ENW-169 Finished initializing snap system.
MSG-10 While running 'run rtl fsm /work/MODULE1/MODULE1':
FSM-9 FSM optimization: 0 successful in total.
MSG-10 While running 'run rtl expression /work/MODULE1/MODULE1':
EXP-4 Labeling datapath cells
EXP-5 Grouping datapath cells into expression models
EXP-7 Carrysave in expression models
EXP-8 Flattening expressions for expression models
EXP-9 Resource sharing over flat expressions
EXP-10 Generating DPF for expression models 
MSG-10 While running 'export volcano snap/MODULE1%fix-rtl-final.volcano -background':
BCK-100 Command "export volcano" is executing in the background.

and error message for part 2:

################### Starting Standard fix rtl ####################

MSG-10 While running 'run rtl fsm /work/MODULE2/MODULE2':
FSM-9 FSM optimization: 0 successful in total.
MSG-10 While running 'run rtl optimize /work/MODULE2/MODULE2':
RTL-3052 ERROR: IEEE Std 1800-2005 [8.13] /work/multiplexor2x1_WIDTH18/multiplexor2x1_WIDTH18/mux_if_1%/C8%/C4 in assignment pattern expression not supported in this release
CMD-56 1 ERROR message and 0 WARNING messages from "run rtl optimize ..."
MSG-10 While running 'export volcano snap/MODULE2-error.volcano':
LAVA-976 WARNING: Overwriting an existing volcano directory.
LAVA-26 Writing library /stdlib
LAVA-26 Writing library /memlib
LAVA-26 Writing library /work
LAVA-26 Writing library /macro_lib
LAVA-900 Successfully froze lava into volcano snap/MODULE2-error.volcano:    1 seconds,    1 on cpu.
QDB-26 Writing QOR monitor data
LAVA-249 Volcano file size: 4.5 MByte (27.8 MB data, Compression = 6.12x)
LAVA-251 Data throughput 16.735 MB/s (1.66 s elapsed)
CMD-56 1 ERROR message and 1 WARNING message from "fix rtl ..."

Module multiplexor2x1 is very simple and really wrote by verilog syntax:

module multiplexor2x1(a,b,sel,z);
parameter WIDTH = 4;
output    [WIDTH-1:0] z;
input     [WIDTH-1:0] a;
input     [WIDTH-1:0] b;
input                 sel;

reg       [WIDTH-1:0] z;

always @(a or b or sel)begin
  case (sel)
    1'b0: z = a ;
    1'b1: z = b ;
  endcase
end
endmodule

Thanks in advance any help

haianh,

 

[haianh]

Solution: start a new talus session after synthesize each part or "refresh" Talus
Command: data delete object /