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I have noticed that power rails are put on metal 2. Metal 1 is not used for signal routing or power routing. Why ?
Is it because at lower technology nodes, there is a lot of signal routing within the std cells so an entire layer (M1) is used up ?
Why are N-well, P-well and power continuity required ?
Hi,
Filler cells are added for n well, pwell and metal 1 continuity. Why should n well p well be continuous ? I understand that Metal 1 should be continuous for min density reasons and EM reasons.
What exactly is power continuity ...
What are line end shortening and phase shift mask ?
As the feature size reduces below 193 nm (imaging wavelength), certain correction are done for better manufacturability and as a compensation for photolithography, etching, planarization and deposition...
time = \[\frac{charge }{current }\]
charge = Capacitance * supply voltage
current = (\[\frac{\mu*Cox*W}{L}\])* (\[{ (VDD-{ V}_{t })}^{2 }\])
Therefore time is inversely proportional to the supply voltage. When the supply voltage decreases due to IR drop, the cell rise and fall time...
Read the rule documents from foundries like TSMC. Read about full custom design and its parameters will help a lot for PDV. Read the first chapter of PD essentials for this. https://www.scribd.com/doc/38215040/Physical-Design-Essentials
Hey,
Lockup latch are used as a synchroniser between two flop from different clock domains (asynchronous clocks) along the scan chain and add in the SI path.
There is a switch in RTL complier to mix compatible clocks in a scan chain for posedge negedge launch capture and if they are of...
Re: How do i reduce the insertion delay of my block?
Hey, the difference in insertion delay is skew. If you add the skew to the insertion delay for a launch flop, you get the insertion delay for the responding capture flop. Simple math.
The metal nets are not perfect a rectangle when seen cross-sectionally but looks like a dish due to CMP https://en.wikipedia.org/wiki/Chemical-mechanical_planarization
This causes shorts between two metal nets and open in a metal net.
Max density and min density will be defined in the lef file...
Re: How do i reduce the insertion delay of my block?
Cumulative skew is not insertion delay. Insertion delay is the time taken for clock to reach the CK pin of the flop from its source. By adding buffers to the path with least buffers in a launch-capture pair of flops, the difference in the...
Re: How do i reduce the insertion delay of my block?
Hey I didn't quite understand what you meant. Can you please elaborate or point me to an website that does ? thanks.
Hello I recently had an interview where I was asked a lot of bit manipulative questions and I wasn't very good at answering them. like for example, how to create a mask, some puzzles like https://www.careercup.com/question?id=20004674
Can anyone here suggest some good links or links to books to...
I am currently doing a project that involves a PLL design using simulink.
The specs are as mentioned. Input frequency: 70MHZ, Loop Bandwidth: 1KHZ.
Could anyone tell me how I can find the values for pd, vco, Loop filter gains (kd, kf and kv) and R1 C1 C2 parameters of the 2nd order lead lag...
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