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Recent content by free1983

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    Help! Chang name fail while using physical compiler

    Hi, all I have encounter a problem that failed to change name when I write to Milkway library. The tool give a infomation like this: change_name -rule verilog Error! Fail to set the object * with name A (port). And my design has no port infomation anymore when I read back the database, How can I...
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    what is a CKBD pattern test of flash memory?

    ckbd flash Hi all, what is a CKBD and ICKBD pattern test of flash memory? how can I do a CKBD or ICKBD programing of a flash memory? Thanks!
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    Abort a DSPF annotate question

    dspf file specification The question could be simpled to this : what is the relationship between "*|I (U3583:A U3583:A I 2.3241e-14 " and "Cg34620 U3583 : A 0 9.8482e-15" ,they all means "pin capacitance",what the differences between them, should thay be added together or only one of them...
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    Abort a DSPF annotate question

    dspf spec Hi All I have a problem abort annotate DSPF file to PrimeTime,I use the read_parasitics command to read in the DSPF file which was generated by STAR-RC.there is a option -pin_cap_included of read_parasitics command,I don't known should use this option whether or not? The MAN PAGE...
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    help : a question about selection of RTOS

    hi guys, which real time operating systems need MMU (Memory Manage Unit)support? and which is not needed? thanks!
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    HELP:need Advanced chip synthesis tutorial of synopsys.

    must need a SOLV NET user ID to download~~:cry:
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    what's the mean of set_mode command?

    Thank u for ur reply does the mode (read or write) defined by the vendor or by customer? can I reset those modes ? Thanks
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    what's the mean of set_mode command?

    synopsys design-compiler set_mode Hi,All there is a command "set_mode" in Synopsys Design Compiler ,the command syntax is : dc_shell> set_mode {read transparent} U1/U2/core so, what the mode "read transparent" mean ? does the every cell in the library has this attribute or definded by the...
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    set_clock_gating_check

    may be this article will help u,"How To Successfully Use Gated Clocking in an ASIC design ,Darren Jones ,SNUG Boston 2002". enjory it. regards
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    How to define max_fanout max_transition max_capacitance ?

    what is meant by max capacitance Typical design rule scenarios are • set_max_fanout and set_max_transition commands • set_max_fanout and set_max_capacitance commands Typically, a technology library specifies a default max_transition or max_capacitance, but not both. To achieve the best result...
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    How to increase the length of each scan chain in DFT?

    DFT help When you finish inserting scan at the top level, write the Standard Test Interface Language (STIL) test protocol file for TetraMAX using the write_test_protocol command. You should also write out a Verilog or VHDL top-level netlist for use in TetraMAX. dc_shell> write_test_protocol...

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