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Recent content by ericyuan

  1. E

    What are the factors that determine the setup time of a flip-flop?

    Flop setup time the DFF setup time is [delay CK->close latch gate] - [delay D->close latch source]
  2. E

    Can you violate both setup and hold time ?

    timing doubt the same launch and capture clock。 the longest launch +shortest capture=>setup。 the shortest launch + longest capture => hold。
  3. E

    Can you violate both setup and hold time ?

    is there any path which violate both setup and hold time?
  4. E

    How does I/O design differ from std cell design?

    I/O Design area? performance? and DFM
  5. E

    What is the H-Tree and what does it do?

    H Tree clock tree structure.... maybe it is a good way to balance the skew...
  6. E

    Difference between Latency and Delay

    what is difference between latency & delay the delay in the clock tree is latency...
  7. E

    What is the best synthesis tool available on the market ?

    Synthesis Tool design compiler.... maybe physical systhesis is another good way to implement the chip
  8. E

    A good paper on power estimation techniques

    it is NOT a practise method,,,, power estimation is a hard work...
  9. E

    How does I/O design differ from std cell design?

    I/O Design reliablity?
  10. E

    How to draw the stick diagram for scan D flipflop?

    Stick Diagram fold the transistor,,,and place the pin for routing 1-2 track, you can draw it on paper,,,,it is an art work:)
  11. E

    critical path in SRAM

    read or write?
  12. E

    TAP controller design specification

    Re: DFT 3x
  13. E

    Tool for taking input directly from backward annotated SAIF file by parsing it

    Re: SAIF doubt what is SAIF?
  14. E

    Gate that can delay a signal in in it's input by delta

    Re: Delay gate should control the PMOS/NMOS drive strength.....
  15. E

    WHy we use NAND gate only in CMOS than NOR gate

    is that why we use sleep(shut down) PMOS? PMOS is better than NMOS in leakage power?(same size)
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