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Hello,
For awhile now I've been battling trying to implement LVDS deserialization in my Spartan-6 with some success. I need to achieve bit-clock rates of 650 MHz in the final implementation, although I'm somewhat limited currently by my FPGA Drigmorn3 evaluation board.
I've been trying to...
That makes sense and I think I can make due with that for a proof-of-concept. Although I'm clearly missing something. This code works in simulation:
//Buffer the input clock to be available for the another bank (limits clock rate to ??)
clock_generator_ddr_s8_diff #(
.S (S)...
I guess more specifically, for the following declarations of datain
NET "datain_p[0]" DIFF_TERM = "TRUE";
NET "datain_p[0]" IOSTANDARD = LVDS_33;
NET "datain_p[0]" LOC = R3;
NET "datain_n[0]" DIFF_TERM = "TRUE";
NET "datain_n[0]" IOSTANDARD = LVDS_33;
NET "datain_n[0]" LOC = T3;
NET...
There are easily accessible clock inputs (I've used one of them for something else) but its on a different connector header than the one I was using to interface the ADC to FPGA. I had designed a board to interface the two and the reason I'm complaining is its going to have to be a little bit...
Oh man thats exactly what I was hoping was not the problem. Routing the ADC's bit rate clock to anything other than the pins I was using is very hard. Is there no way to route the bit rate clock into the pins I was using?
That was a very helpful explanation, thank you. However, I still have this not routeable issue.
The project I'm currently trying to route and place is a very simple project. All I did was take the files from XAPP1064, make some small changes to the number of inputs and outputs, and create a...
Should you really be declaring the negative side of differential pairs? Isn't it implied by the LOC of the positive side?
Scott
---------- Post added at 22:05 ---------- Previous post was at 21:56 ----------
Also adding that line at the very first line of each of the modules provided by...
It synthesizes fine, translates fine, maps fine, and barfs on the Place and Route. Removing the XOR so that those two lines read as
assign iob_data_in_p = rx_clk_in_p; // Invert clock as required
assign iob_data_in_n = rx_clk_in_n; // Invert clock as required
didn't change anything. Can...
I was on vacation for the last week and a half and just started working on this again. Before leaving I managed to show in simulation that all of the bitslipping was working and all was good. However, when going through the implement design stage I got an unrouteable design. Thinking maybe it...
Ok changing it from a 1ps update to a 1ns update made it work. I guess the simulator was telling me the FPGA can't operate at a THz which is reasonable. My bits don't seem to make any sense but at least I'm getting something out.
Does my bitslip logic seem correct?
---------- Post added at...
My basic problem is that I would like to clock my FPGA at a very specific frequency multiple (over a million) of an incoming signal. This incoming signal is wall power, so it is 60 Hz, plus or minus, and slowly varying. My original approach was to purchase a VXCO at this frequency that had the...
Here is my current code for the module serdes_1_to_n_clk_ddr_s8_diff. I do not think I changed anything from the provided version in the XAPP.
timescale 1ps/1ps
module serdes_1_to_n_clk_ddr_s8_diff (clkin_p, clkin_n, rxioclkp, rxioclkn, rx_serdesstrobe, rx_bufg_x1) ;
parameter integer S = 8...
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