EnderW4785
Member level 1
I guess more specifically, for the following declarations of datain
NET "datain_p[0]" DIFF_TERM = "TRUE";
NET "datain_p[0]" IOSTANDARD = LVDS_33;
NET "datain_p[0]" LOC = R3;
NET "datain_n[0]" DIFF_TERM = "TRUE";
NET "datain_n[0]" IOSTANDARD = LVDS_33;
NET "datain_n[0]" LOC = T3;
NET "datain_p[1]" DIFF_TERM = "TRUE";
NET "datain_p[1]" IOSTANDARD = LVDS_33;
NET "datain_p[1]" LOC = T4;
NET "datain_n[1]" DIFF_TERM = "TRUE";
NET "datain_n[1]" IOSTANDARD = LVDS_33;
NET "datain_n[1]" LOC = V4;
What inputs are valid for clkin_p and clkin_n? I've tried a bunch of "clock" eligible pins and it seems to always complain that they are not on the same half-bank. When I don't declare where clkin should be in the ucf it place and routes just fine.
NET "datain_p[0]" DIFF_TERM = "TRUE";
NET "datain_p[0]" IOSTANDARD = LVDS_33;
NET "datain_p[0]" LOC = R3;
NET "datain_n[0]" DIFF_TERM = "TRUE";
NET "datain_n[0]" IOSTANDARD = LVDS_33;
NET "datain_n[0]" LOC = T3;
NET "datain_p[1]" DIFF_TERM = "TRUE";
NET "datain_p[1]" IOSTANDARD = LVDS_33;
NET "datain_p[1]" LOC = T4;
NET "datain_n[1]" DIFF_TERM = "TRUE";
NET "datain_n[1]" IOSTANDARD = LVDS_33;
NET "datain_n[1]" LOC = V4;
What inputs are valid for clkin_p and clkin_n? I've tried a bunch of "clock" eligible pins and it seems to always complain that they are not on the same half-bank. When I don't declare where clkin should be in the ucf it place and routes just fine.