Clock PLL'ing in a Spartan-6 FPGA

[EnderW4785]

My basic problem is that I would like to clock my FPGA at a very specific frequency multiple (over a million) of an incoming signal. This incoming signal is wall power, so it is 60 Hz, plus or minus, and slowly varying. My original approach was to purchase a VXCO at this frequency that had the largest pull range I could find (+/-200ppm), divide that frequency down in the FPGA and output the xor of the divided down frequency signal with the incoming signal. Then as with most PLL's, I put that xor signal through a low pass filter and had the resulting voltage drive my VXCO.

It worked, sort of. The main problem is that wall power varied from 60Hz too much for the pull range of my VXCO. The next logical step could be to purchase a VCO and do the same thing, although the pull range of VCO's is incredibly large and I'm concerned this won't be stable.

Is there a better approach to solving this problem? I've been reading about the different ways to PLL a clock and maybe I should be doing more of this in the digital domain? Is it possible to generate this desired clock signal within the FPGA itself and have that clock my other operations?

Any help would be appreciated.

 

[joelby]

Have a look into some of the GPS oscillator synchronisation systems. The algorithm I use is this:

- Use an OCXO with a fairly small pull range
- Clock a timer with the OCXO's output (10 MHz)
- Every sixteen times I get a 1 PPS GPS signal, save the timer value (I use a PIC's timer peripheral for these two steps, but it would be trivial to do in an FPGA too)
- Divide the timer value by 16 and compare it to 10e7. If it's higher, send a lower value to the DAC connected to the OCXO control voltage, etc.

I guess the question is how fast you want to track the 60 Hz signal. In my case I'm more interested in long-term stability than tracking small changes in the PPS signal. You might find that your ADC doesn't like having its sample clock changed quickly, as it'll have its own internal PLL. I'm not sure the parts I've used specify what their PLL lock times are, or if they even have a PLL lock output (but I haven't needed to know)

Also you might want to consider what you want to do with the data you're capturing. I know you said you wanted to sample at an exact multiple of the signal frequency, but maybe it would be easier to just get close enough, oversample, and post-process the data, since you'll be able to see the 60 Hz signal in your sample anyway? (or you could superimpose it, or sample it simultaneously).

I don't think that an FPGA's internal clocking resources will be adequate, and they tend to make horrible clock sources for ADCs.