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Recent content by eeeraghu

  1. E

    slack optimization using RTL compiler

    Hi, As u r having a slack of -16.5 ns in 10ns clk period which is more than a clock period, the tool high effort and other simple change of gates or buffering the path wouldn't help much, as there is a huge slack and the tool can only minimize upto certain point. The other options wud be change...
  2. E

    FIFO DEPTH and BURST SIZE!

    best case/good case = write data is always ready whenever the fifo's full is 0, worst case = write data writing on its required time. Burst is sequence of data as given in ur requirement 8 locations so 8 different data's in sequence back to back. i.e 1st-> 2nd -> ....... 8th also said as 8 beat...
  3. E

    FIFO DEPTH and BURST SIZE!

    Hi considering the burst of above i/p & o/p requirements and assuming each ip data freq is at 50 MHz (i.e total 8 * 20ns = 160 ns) then for a best case the depth wud be 8 & for worst case depth wud be 32. This is my understanding only.
  4. E

    Differences between LVT and HVT Cells, architecture and advantages

    **broken link removed** please refer to the above link lot of discussions in the board. Thanks &&&&
  5. E

    AMBA AXI Interface questions

    Yes u can send the second address without waiting for the response channel if the slave supports the multiple outstanding address. This depends on the slave implementation of ordering model. check the section 8.1 section of AXI spec about ordering model. hope it clears u.
  6. E

    AMBA AXI Interface questions

    Hi, yes without receiving ready for the current address, u cannot send the second address either it is outstanding or doesn't support outstanding feature.
  7. E

    design and analysis of image segmention in region growing using vhdl and vlsi

    Hi, as segmentation is defined as to separate out the regions of the image corresponding to objects in which we are interested, from the regions of the image that correspond to background. There are many segmentation algorithms which are available the basic being thresholding --> so in a...
  8. E

    AXI throughput & latency

    master and slave are 2 different entities here, so if u have designed them directly such that the o/p of that particular master is input to the particular slave such as the IP = (master + slave), the throughput = total no of bits per cycle at the slave o/p and latency is the no of cycles taken...
  9. E

    Thank you / New look and feel OF EDA board

    good looks refreshing
  10. E

    Design Compiler warning OPT-1206

    design compiler -edges after boundary optimization use set register merging as false for that particular register inorder not to remove or merge that particular register for particular reasons.
  11. E

    Parallel Read and write in AHB-AXI bridge

    axi write read does your AHB2AXI bridge support two ahb masters, if so yes, the axi interconnect can drive read & write.
  12. E

    Logic synthesis using Design Compiler

    design compiler multiplier Hi, DC uses design ware multiplier available if it sees a *, which itself has a large delay. so either use a multi cycle path between the path where multiplier is a critical path. regards ~
  13. E

    is this a pipeline design ?

    not exactly, if outputs of each module are registered it may not be pipeline. if in a particular path a point is registered and the handshake and control of that point must also act exactly & affect accordingly. Moreover pipelined architecture is what that current input does not affect the...
  14. E

    Need info about the details for uRM

    Re: uRM its something like the rules & guidelines followed for a particular IP, so that any one else can use it in any form of the IP. therefore the IP is complaince with uRM. for example implementing a built in self test kind of thing and use it.
  15. E

    without wire load model

    for simply synthesizing and checking the timing reports, without any WLM use the clock uncertainity level to >20% so that whatever the delays & extra R C & other cancel out w r t WLM when there is >20% of uncertainity. Hope iam true.
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