Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by dumindu89

  1. D

    [SOLVED] Help me to fix these two errors in this VHDL code

    I am getting following 2 errors when I am compiling my VHDL code. Here is the code. (I highlighted the line that causing these errors) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.ALL; entity final is port(...
  2. D

    Help me to lock this pll

    Hello! I implemented a pll using 74s124 vco, Altera MAX II CPLD (programmble divider, referance frequency, XOR gate for the phase comparator) and a 2 nd order low pass filter. The referance frequency is 25 kHz and the free running frequency of the VCO is 30 MHz. The desired range is 22 MHz- 27...
  3. D

    Amplifier design using BFR540 transistor

    Amplifier design using BFR520 transistor Hello I need to make a transistor amplifier which has a voltage gain of 15 at 100 MHz. I have the BFR520 NPN wide band transistor (fT = 9 GHz). 1. Is it possible to make this amplifier using general calculations (by calculating RB1, RB2, RE, RE for...
  4. D

    Run more than one vhdl codes in a single CPLD

    I just wrote the whole VHDL program as follows and it compliled successfully. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity final is port( clk_in_for_fixed,clk_in_for_programmable,xor_in_1,xor_in_2,not1_in1,not2_in2: in std_logic; clk_out_fixed...
  5. D

    Run more than one vhdl codes in a single CPLD

    I want to run few vhdl codes (more than one process) in the same CPLD parallelly (MAX II EPM240T100C5). Simply I have seperate vhdl codes for a fixed frequency divider, programmable frequency divider, xor gate,not gate. I want to run them parallelly in the same CPLD. How can I do that?
  6. D

    std_logic_vector to integer in VHDL

    Here is the full code.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity programmable_divider is port( clk : in std_logic; clk_out : out std_logic; divide_value : in std_logic_vector (9 downto 0) ); end divider; architecture Behavioral of divider is signal...
  7. D

    std_logic_vector to integer in VHDL

    Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion. But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider...
  8. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    I were able to compile the code for programmable divider but I it took more than 30 minutes for the simulation (vector waveform) and still couldn't get the simulation report (but no errors encountered) in Quartus II 7.2 sp3 web edition. Therefore I gave up the simulation. I don't know why it...
  9. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    I got the following code for fixed division from here >> https://vhdlguru.blogspot.com/2011/03/clock-frequency-converter-in-vhdl.html And modified it for programmable division as follows. what do you think? I have a doubt in std_logic_vector to integer conversion. Does my code for the...
  10. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    First of all I got an error when I compile the following vhdl code which is a fixed frequency divider through Quartus II Error (10309): VHDL Interface Declaration error in div3.vhd(25): interface object "clk_out" of mode out cannot be read. Change object mode to buffer. what is this issue?
  11. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    My frequency dividing range for the programmable divider is from 880 to 1080. Anyways, I am struggling to write a VHDL code for an appropriate prescaler. Can you show me a sample code?
  12. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    OK. :smile: Then the next step is implementing the programmable divider. Hmm.. What is the easiest method for that?
  13. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    Hello! I decided to write the code using VHDL. I found a VHDL code for a frequency divider (divided by 25) and I modified it to divide the frequency by 80. (I need a divided by 80 fixed divider too). So what about this code? Is it fine? I have two points in this code to understand. why do we...
  14. D

    Code for division in VHDL

    Re: vhdl division Anyone have a VHDL code for a programmable divider which can change the dividing frequency by a integer number from outside (Let's say DIP switches will give the dividing frequency)
  15. D

    Verilog code for decade down counter with asynchronous parallel load and borrow

    Help me to write the verilog code for a decade down counter with asynchronous parallel load and borrow. The operation is similar to the 74192 IC. I can write the code for decade down counter. But I have no idea how to implement the parallel load inputs and the borrow output. :sad: Please help...
See more

Part and Inventory Search

Back
Top