Verilog code for decade down counter with asynchronous parallel load and borrow

[dumindu89]

Help me to write the verilog code for a decade down counter with asynchronous parallel load and borrow. The operation is similar to the 74192 IC.

I can write the code for decade down counter.
But I have no idea how to implement the parallel load inputs and the borrow output. :sad:

Please help me to write the complete verilog code for this. Any suggestion? ( I am using Altera MAX II - EPM240T200C5N CPLD)

 

[mrflibble]

How about showing the code you have so far?

 

[dumindu89]

Hello!
I decided to write the code using VHDL.

I found a VHDL code for a frequency divider (divided by 25) and I modified it to divide the frequency by 80. (I need a divided by 80 fixed divider too).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divby_80 is
Port (
clk : in std_logic;
reset: in std_logic;
clk_out : out std_logic

);
end divby_80;

architecture divby_80_a of divby_80 is
process(reset,clk)
begin
if (reset='0') then
count<=0;
clk_out<='0';
elsif rising_edge(clk) then
if (count=79) then
clk_out<=NOT(clk_out);
count<=0;
else
count<=count+1;
end if;
end if;
end process;
end divby_80_a;

So what about this code? Is it fine?
I have two points in this code to understand.
why do we use "clk_out<=NOT(clk_out);" and why do we use a reset?
Once I finished the code for this fixed divider I can move to the programmable divider which is more complex.

 

[mrflibble]

Better make that 3 points to understand. Because you have just implemented a divide by 160. Counting to 80 and then inverting the clock result in a period of 160 counts. Adjust accordingly (count to 40, not 80) and everything shall be peachy!

Also ... "why do we use "clk_out<=NOT(clk_out);" ... uhm, well, you want an output that actually changes a la 1010101010101. If you would not not, then you do not get your clock.

"and why do we use a reset?" Why not? Also, the reset is put there specifically to have some people realize they should run to the library to get a book on digital design. ;-) You do the reset to get your system in a known state. In this case when the reset is asserted, count gets initialized to 0. Oh and clk_out is set to 0 as well.

 

[dumindu89]

Better make that 3 points to understand. Because you have just implemented a divide by 160. Counting to 80 and then inverting the clock result in a period of 160 counts. Adjust accordingly (count to 40, not 80) and everything shall be peachy!

Also ... "why do we use "clk_out<=NOT(clk_out);" ... uhm, well, you want an output that actually changes a la 1010101010101. If you would not not, then you do not get your clock.

"and why do we use a reset?" Why not? Also, the reset is put there specifically to have some people realize they should run to the library to get a book on digital design. ;-) You do the reset to get your system in a known state. In this case when the reset is asserted, count gets initialized to 0. Oh and clk_out is set to 0 as well.

OK. :smile:

Then the next step is implementing the programmable divider. Hmm.. What is the easiest method for that?

 

[mrflibble]

Where you have "if (count=79) then" now, you make it "if (count=prescaler) then" etc. And this "prescaler" is for example an 8-bit wide input that you have to add to your module.

Then setting prescaler to 39 will result in 40 counts, which gets you a divide by 80.

 

[dumindu89]

Where you have "if (count=79) then" now, you make it "if (count=prescaler) then" etc. And this "prescaler" is for example an 8-bit wide input that you have to add to your module.

Then setting prescaler to 39 will result in 40 counts, which gets you a divide by 80.

My frequency dividing range for the programmable divider is from 880 to 1080.
Anyways, I am struggling to write a VHDL code for an appropriate prescaler. Can you show me a sample code?

 

[mrflibble]

I could. But I won't. All you need in the above is add an extra "prescaler" input to your module like I suggested before. Why do I not give you code for that? Well, if you don't know how to do that then there will be more challenges for you. So your best bet is to find a few vhdl tutorials and see how you can add an input to that module.

I am all about laziness, but this is not the particular brand of laziness I tend to enable. Besides, with a bit of luck someone else will give you an example.

Anyways, the 3 vhdl concepts you should be googling are: integer, std_logic and std_logic_vector.

 

[dumindu89]

First of all I got an error when I compile the following vhdl code which is a fixed frequency divider through Quartus II

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divby_80 is
Port (
clk : in std_logic;
reset: in std_logic;
clk_out : out std_logic

);
end divby_80;

architecture divby_80_a of divby_80 is
process(reset,clk)
variable count : integer;
begin
if (reset='0') then
count:=0;
clk_out<='0';
elsif rising_edge(clk) then
if (count=39) then
clk_out<=NOT(clk_out);
count<=0;
else
count:=count+1;
end if;
end if;
end process;
end divby_80_a;

Error (10309): VHDL Interface Declaration error in div3.vhd(25): interface object "clk_out" of mode out cannot be read. Change object mode to buffer.

what is this issue?

 

[mrflibble]

The issue is lack of googling: https://www.google.com/search?q=int...+cannot+be+read.+Change+object+mode+to+buffer.

There we go: https://www.alteraforum.com/forum/showthread.php?t=25819

 

[dumindu89]

I got the following code for fixed division from here >> https://vhdlguru.blogspot.com/2011/03/clock-frequency-converter-in-vhdl.html

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity clk_gen is
port( Clk : in std_logic;
Clk_mod : out std_logic;
divide_value : in integer
);
end clk_gen;

architecture Behavioral of clk_gen is

signal counter,divide : integer := 0;

begin

divide <= divide_value;

process(Clk)
begin
if( rising_edge(Clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
Clk_mod <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
Clk_mod <= '1';
else
Clk_mod <= '0';
counter <= 0;
end if;
end if;
end process;

end Behavioral;

And modified it for programmable division as follows.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity divider is
port( clk : in std_logic;
clk_out : out std_logic;
divide_value : in std_logic_vector (9 downto 0)
);
end divider;

architecture Behavioral of divider is

signal counter,programmable_divide : integer := 0;

begin

programmable_divide <= to_integer(unsigned(divide_value(9 downto 0)));

process(clk)
begin
if( rising_edge(clk) ) then
if(counter < programmable_divide/2-1) then
counter <= counter + 1;
clk_out <= '0';
elsif(counter < programmable_divide-1) then
counter <= counter + 1;
clk_out <= '1';
else
clk_out <= '0';
counter <= 0;
end if;
end if;
end process;

end Behavioral;

what do you think?
I have a doubt in std_logic_vector to integer conversion. Does my code for the particular conversion have any issues?

 

[dumindu89]

I were able to compile the code for programmable divider but I it took more than 30 minutes for the simulation (vector waveform) and still couldn't get the simulation report (but no errors encountered) in Quartus II 7.2 sp3 web edition. Therefore I gave up the simulation. I don't know why it taking lot of time to simulate that code.

What is the wrong? :sad: