std_logic_vector to integer in VHDL

[dumindu89]

Hello I am trying to convert a std_logic_vector to integer. Here is how I did the std_logic_vector to integer conversion.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity programmable_divider is
port( clk : in std_logic;
clk_out : out std_logic;
divide_value : in std_logic_vector (9 downto 0)
);
end programmable_divider;

architecture Behavioral of programmable_divider is
signal counter,programmable_divide: integer := 0;
begin
programmable_divide <= to_integer(unsigned(divide_value(9 downto 0)));

But this didn't gave the correct output when I enter 4 as binary (0000000100) in the simulation via Quartus II 7.2 (The device is : MAX II EPM240T100C5). I mean the divider should divide the clk by 4.
Instead of that I observed around divide by 5 or 6.

Please help me to solve this case.

 

[dftrtl]

Can you confirm what is the exact output result you have observed ?

 

[alexan_e]

I think the error is probably due to the implementation of the counter/divider rather than the conversion.

 

[dumindu89]

Here is the full code..

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity programmable_divider is
port( clk : in std_logic;
clk_out : out std_logic;
divide_value : in std_logic_vector (9 downto 0)
);
end divider;
 
architecture Behavioral of divider is
 
signal counter,programmable_divide : integer := 0;
 
begin
 
programmable_divide <= to_integer(unsigned(divide_value(9 downto 0)));
 
process(clk)
begin
if( rising_edge(clk) ) then
if(counter < programmable_divide/2-1) then
counter <= counter + 1;
clk_out <= '0';
elsif(counter < programmable_divide-1) then
counter <= counter + 1;
clk_out <= '1';
else
clk_out <= '0';
counter <= 0;
end if;
end if;
end process; 
 
end Behavioral;

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If there is no errors in the code may I program the CPLD and check the result? Because few my friends told that though they get these type of simulation resulrts they were able to get the correct outputs in real implementation without errors.