Help me to lock this pll

[dumindu89]

Hello!
I implemented a pll using 74s124 vco, Altera MAX II CPLD (programmble divider, referance frequency, XOR gate for the phase comparator) and a 2 nd order low pass filter. The referance frequency is 25 kHz and the free running frequency of the VCO is 30 MHz. The desired range is 22 MHz- 27 MHz and it is adjustable by the Programmable divide by N counter (25kHzxN). Although I implemented the PLL it doesn't lock.

How I lock it? Please let me know.

 

[BradtheRad]

Did you try the same procedure at a lower frequency? Using clean square waves?

For testing purposes, it may be necessary to start with a situation which makes it easy to get successful results.