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Hi all,
I was going through the TSMC 40nm pcell inductor model and I think I can't see any ground or floating shield.
There is a subcell inside the inductor layout pcell view which is called "dummy_loop_diff_DM_sym_ind". I think that subcell relates with OD/PO (red and blue colour) dummy...
Hi all,
What is the best floorplan of a LC-VCO 12GHZ in terms of minimizing the parasitic inductance of the connection tracks? Should I connect the GM active (-R) circuit just after the inductor legs or just after the capacitor bank ?
reminder: Connection tracks = the 2 main top level wide...
Hi dick_freebird,
thanks for your reply. I appreciate your answer.
Yes, my bias scheme is a current mirror.
What do you mean by saying that I can use a replica bias scheme which forces an equivalent CML stage's output
across termination to be a particular amplitude? Can you give an example...
Hi all,
I would like to ask you two questions.
1) If the the pull-up resistor is 50 Ohm, what conditions set the bias current (current tail) of the differential pair?
I know that ISS*50 Ohm should be < Vth of the differential pair for keeping the diff. pair in saturation.
So, if I do not...
Hi sophiante,
Thanks for your reply. I have not thought about this. Could you be more specific or is there any paper or book from which I can have a look at it?
Thanks
Hi all,
Just a general question of my knowledge of dividers.
So far, I know that a "divider-by-2" (when the VCO freq is high, the divider by 2 is analog) is needed because its output signal gives 50% duty cycle and also the programmable digital divider (prescaler) can functions better with...
Hi KlausST,
Phase margin is very good (over PVTs and MC). is around 90 degree. I am not talking about this. My mistake. I did not explain exactly. I have a circuit which feeds (its power supply pin) the output of LDO with high (50mA current step) current pulses with quite fast pace (period...
Hi all,
I am working on a LDO regulator (CMOS process technology) circuit for a project. I would like to ask analog design engineers, how can I protect the circuits from over-voltages that may happen at the output of LDO?To be more specific,this LDO output provides power supply to circuits...
Hi all,
Thanks for your reply. The problem was solved. Actually, the constant -GM- bias circuit (inside the VCO core block) was not stable. That was the reason of this high spike. Anyway, thanks for your interest.
Hi all
I face a strange issue when simulating the LDO together with a LC VCO. I want to calculate the PSRR at the output of LDO connected together with the VCO. I run AC simlation
and I take quite strange simulations results( maybe dangerous) at the LDO voltage output. I attach you a...
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