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VCO layout floorplan - Minimizing parasitic inductance

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dtz_lou

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Hi all,

What is the best floorplan of a LC-VCO 12GHZ in terms of minimizing the parasitic inductance of the connection tracks? Should I connect the GM active (-R) circuit just after the inductor legs or just after the capacitor bank ?

reminder: Connection tracks = the 2 main top level wide metal tracks on which inductor, capacitor bank and GM circuit are hooked up

In other words, as we look a LC VCO top level layout view from top to bottom, which sequence is best in order to get less parasitic inductance:

TOP to BOTTOM VIEW

1) Inductor -->capacitor bank ( includes analog tuning cap.+discrete tuning cap.) -->GM circuit OR
2) Inductor --> GM circuit --> capacitor bank( includes analog tuning+discrete tuning)


For the case 1), I noticed that if I place the output pins at the bottom edge of track connections, I am seeing more inductance (L_schematic+L_track_connections) using EMX tool.

Any advise or opinion is more than welcome.


Thanks in advance
 

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