[SOLVED] LDO output voltage connected on VCO (represents the power supply of VCO)

[dtz_lou]

Hi all

I face a strange issue when simulating the LDO together with a LC VCO. I want to calculate the PSRR at the output of LDO connected together with the VCO. I run AC simlation

and I take quite strange simulations results( maybe dangerous) at the LDO voltage output. I attach you a screenshot for getting a better feeling about the possible problem.

The architecture of VCO is a LC nmos cross-coupled with a PMOS current source throw the bias current in the inductor. there is a big decoupling capacitor connected between the LDO

voltage output and ground (around 100pF) As a result an RLC resonator circuit is accomplished. and the peak arises at frequency F=1/(2*pi*sqrt(LC))\[\approx\]24MH.

Do you have any comment on this? Is it dangerous? And if yes how can I verify it?

 

[KlausST]

Hi,

can you show us the schematic, please.

28 dBV are about 25V. not dangerous.

Klaus

 

[Dominik Przyborowski]

Probably this peak amplitude is much higher (depends to your ac simulation step) and it could seriously deteriorate overall performance of system.
Check on transient simulation the behaviour of LDO output.

 

[dtz_lou]

Hi all,

Thanks for your reply. The problem was solved. Actually, the constant -GM- bias circuit (inside the VCO core block) was not stable. That was the reason of this high spike. Anyway, thanks for your interest.